公开(公告)号：US20090049686A1

公开(公告)日：2009-02-26

申请号：US12081858

申请日：2008-04-22

申请人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

发明人： Hwa-Sun Park ,  Sung Yi ,  Sang-Chul Lee ,  Jong-Woon Kim ,  Yul-Kyo Chung

IPC分类号： H05K3/30

CPC分类号： H05K1/185 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H05K1/056 ,  H05K3/445 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/1469 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139

摘要： A method of manufacturing a component-embedded printed circuit board is disclosed. The method includes: forming a blind hole in the first metal layer such that the first insulation layer is exposed, for a metal-clad laminate that includes a first insulation layer stacked over a first metal layer, securing a component to the first insulation layer by embedding the component in the blind hole, stacking a second insulation layer and a second metal layer on either side of the metal-clad laminate, and forming circuit patterns by removing portions of the metal layers.

摘要翻译： 公开了一种制造嵌入元件的印刷电路板的方法。 该方法包括：在第一金属层上形成盲孔以使第一绝缘层暴露，对于包覆层叠在第一金属层上的第一绝缘层的覆金属层压板，将部件固定到第一绝缘层上 将所述部件嵌入所述盲孔中，在所述覆金属层压板的任一侧堆叠第二绝缘层和第二金属层，以及通过去除所述金属层的一部分来形成电路图案。

公开(公告)号：US20090025195A1

公开(公告)日：2009-01-29

申请号：US12081862

申请日：2008-04-22

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G9/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 公开了一种制造电容器嵌入式PCB的方法。 该方法可以包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US07037739B2

公开(公告)日：2006-05-02

申请号：US10751858

申请日：2004-01-06

申请人： Young Tae Byun ,  Hwa Sun Park ,  Seok Lee ,  Deok Ha Woo ,  Jong Chang Yi

发明人： Young Tae Byun ,  Hwa Sun Park ,  Seok Lee ,  Deok Ha Woo ,  Jong Chang Yi

IPC分类号： H01L21/00

CPC分类号： G02F1/025 ,  G02F2001/0152 ,  G02F2001/0154 ,  G02F2202/102 ,  G02F2203/50

摘要： A fabrication method of an epilayer structure for InGaAsP/InP ridge waveguide phase modulator with high phase modulation efficiency. It relates to a P-p-n-N InGaAsP/InP ridge waveguide phase modulator fabricated to be that the phase change of the TE-mode is linearly proportional to the reverse bias voltage at 1.55 μm wavelength. A method for fabricating an epilayer structure for achieving the optical confinement in the vertical direction of an InGaAsP/InP waveguide phase modulator, characterized by comprising the steps of: forming a first cladding layer of N-InP on an N+-InP substrate; forming a first waveguide layer of n-InGaAsP and a second waveguide layer of p-InGaAsP in sequence on the first cladding layer; forming a second cladding layer of P-InP and a third cladding layer of P-InP in sequence on the second waveguide layer; and forming an electrode layer of p+InGaAs on the third cladding layer.

摘要翻译： 具有高相位调制效率的InGaAsP / InP脊波导相位调制器的外延层结构的制造方法。 它涉及一种P-p-n-N InGaAsP / InP脊波导相位调制器，其制造为TE模式的相变与1.55mum波长处的反偏压成线性比例。 一种用于制造用于实现InGaAsP / InP波导相位调制器的垂直方向上的光限制的外延层结构的方法，其特征在于包括以下步骤：在N + 1上形成N-InP的第一包层， SUP> -InP底物; 在第一包层上依次形成n-InGaAsP的第一波导层和p-InGaAsP的第二波导层; 在第二波导层上依次形成P-InP的第二包层和P-InP的第三包层; 以及在所述第三覆层上形成p + + InGaAs的电极层。

公开(公告)号：US09000593B2

公开(公告)日：2015-04-07

申请号：US13568208

申请日：2012-08-07

申请人： Su Jeong Suh ,  Hwa Sun Park ,  Hyeong Chul Youn

发明人： Su Jeong Suh ,  Hwa Sun Park ,  Hyeong Chul Youn

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/495 ,  H01L23/14 ,  H01L33/64

CPC分类号： H01L33/647 ,  H01L23/142 ,  H01L23/49562 ,  H01L33/64 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/4918 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00014

摘要： A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.

公开(公告)号：US08166653B2

公开(公告)日：2012-05-01

申请号：US12801870

申请日：2010-06-29

申请人： Hwa Sun Park ,  Tae Eui Kim

发明人： Hwa Sun Park ,  Tae Eui Kim

IPC分类号： H01K3/10

CPC分类号： H05K1/167 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09481 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of manufacturing a printed circuit board (PCB) having embedded resistors, including providing a PCB on which internal layer circuit patterns, including electrode pads, are formed; layering insulating layers on the PCB; forming first via holes on the electrode pads and simultaneously forming second via holes at predetermined locations on the internal layer circuit patterns; forming contact pads for connecting the electrode pads with resistors by filling the first via holes with oxidation-resistant conductive material and flattening the oxidation-resistant conductive material; forming the resistors so that ends of each resistor are connected to two respective contact pads, which are spaced apart from each other; forming circuit patterns on the PCB, in which the second via holes are formed; and layering insulting layers on the PCB having the formed circuit patterns, and forming external layer circuit patterns.

摘要翻译： 一种具有嵌入式电阻器的印刷电路板（PCB）的制造方法，其特征在于，提供形成有包含电极焊盘的内层电路图案的PCB; 在PCB上分层绝缘层; 在电极焊盘上形成第一通孔并同时在内层电路图形上的预定位置形成第二通孔; 形成用于通过用耐氧化导电材料填充第一通孔并使抗氧化导电材料变平的方式将电极焊盘与电阻器连接的接触焊盘; 形成电阻器，使得每个电阻器的端部连接到彼此间隔开的两个相应的接触焊盘; 在PCB上形成电路图案，其中形成第二通孔; 以及在PCB上具有形成的电路图案的层叠绝缘层，以及形成外部层电路图案。

公开(公告)号：US20100097770A1

公开(公告)日：2010-04-22

申请号：US12406636

申请日：2009-03-18

申请人： Hwa-Sun Park ,  Yul-Kyo Chung ,  Jong-Man Kim ,  One-Cheol Bae

发明人： Hwa-Sun Park ,  Yul-Kyo Chung ,  Jong-Man Kim ,  One-Cheol Bae

IPC分类号： H05K1/16 ,  H05K3/46 ,  H05K3/00 ,  H05K1/00

CPC分类号： H05K1/185 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2225/06524 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0269 ,  H05K3/305 ,  H05K3/386 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/09918 ,  H05K2201/10515 ,  H05K2203/063 ,  H05K2203/066 ,  Y10T156/1052

摘要： Disclosed are a printed circuit board and a manufacturing method thereof. The manufacturing method of a printed circuit board includes: mounting an electronic device on an upper surface of an adhesive layer; laminating an insulator on an upper side of the electronic device and a lower side of the adhesive layer, respectively, such that the electronic device is buried; and forming a circuit pattern and a via on the insulator.

摘要翻译： 公开了一种印刷电路板及其制造方法。 印刷电路板的制造方法包括：将电子器件安装在粘合剂层的上表面上; 分别在电子设备的上侧和粘合剂层的下侧层叠绝缘体，使得电子器件被埋置; 并在绝缘体上形成电路图案和通孔。

公开(公告)号：US07886414B2

公开(公告)日：2011-02-15

申请号：US12081862

申请日：2008-04-22

申请人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

发明人： Woon-Chun Kim ,  Sung Yi ,  Hwa-Sun Park ,  Hong-Won Kim ,  Dae-Jun Kim ,  Jin-Seon Park

IPC分类号： H01G7/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/0195 ,  H05K2201/09672 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49167

摘要： A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

摘要翻译： 公开了一种制造电容器嵌入式PCB的方法。 该方法可以包括制造具有形成在电介质层的一侧上的至少一个内部电极的电容器基板; 将半固化绝缘层与芯层的一侧对准，并将电容器基板与半固化绝缘层对准，使得内电极面向半固化绝缘层; 并且集中地堆叠芯层，半固化绝缘层和电容器基板。

公开(公告)号：US20130037955A1

公开(公告)日：2013-02-14

申请号：US13568208

申请日：2012-08-07

申请人： Su Jeong SUH ,  Hwa Sun Park ,  Hyeong Chul Youn

发明人： Su Jeong SUH ,  Hwa Sun Park ,  Hyeong Chul Youn

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L33/647 ,  H01L23/142 ,  H01L23/49562 ,  H01L33/64 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/4918 ,  H01L2933/0066 ,  H01L2933/0075 ,  H01L2924/00014

摘要： A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.

公开(公告)号：US20120152886A1

公开(公告)日：2012-06-21

申请号：US13403211

申请日：2012-02-23

申请人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

发明人： Woon-Chun KIM ,  Sung Yi ,  Hwa-Sun Park ,  Sang-Chul Lee ,  Jong-Woo Han ,  Young-Do Kweon

IPC分类号： H01G13/00

CPC分类号： H05K1/162 ,  H05K3/108 ,  H05K3/386 ,  H05K3/387 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09672 ,  Y10T428/24355

摘要： A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board.

摘要翻译： 一种制造电容器嵌入式印刷电路板的方法，该方法包括提供其上第一金属层，电介质层和粘合树脂层按顺序堆叠的基板; 蚀刻第一金属层的一部分以形成第一电极和第一电路图案; 通过插入绝缘树脂层将形成有第一电极的基板的表面压在芯板上; 在所述粘合树脂层上形成第二电极和第二电路图案; 在所述基板上堆叠绝缘板，使得所述第二电极和所述第二电路图案被覆盖; 以及在所述绝缘板上形成第三电路图案。

公开(公告)号：US20110048780A1

公开(公告)日：2011-03-03

申请号：US12860301

申请日：2010-08-20

申请人： Jin-Soo Jeong ,  Doo-hwan Lee ,  Hwa-Sun Park ,  Jae-Kul Lee ,  Yul-Kyo Chung

发明人： Jin-Soo Jeong ,  Doo-hwan Lee ,  Hwa-Sun Park ,  Jae-Kul Lee ,  Yul-Kyo Chung

IPC分类号： H05K1/16 ,  H05K3/10

CPC分类号： H05K3/007 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/0554 ,  H05K2203/1572 ,  Y10T29/49124 ,  H01L2924/00

摘要： A method of processing a cavity of a core substrate is disclosed. The method of processing a cavity of a core substrate in accordance with an embodiment of the present invention can include: forming a first processing area on one surface of a core substrate, the first processing area being demarcated by a circuit pattern; forming a second processing area on the other surface of the core substrate, the second processing area being demarcated by a circuit pattern; and processing a cavity by removing the entire first processing area from the one surface of the core substrate.

摘要翻译： 公开了一种处理芯基板的空腔的方法。 根据本发明的实施例的处理芯基板的空腔的方法可以包括：在芯基板的一个表面上形成第一处理区域，第一处理区域由电路图案划定; 在所述芯基板的另一表面上形成第二处理区域，所述第二处理区域由电路图案划定; 以及通过从芯基板的一个表面去除整个第一处理区域来处理空腔。