公开(公告)号：US20090213526A1

公开(公告)日：2009-08-27

申请号：US12390237

申请日：2009-02-20

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Chen-Hsuan Chiu

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Chen-Hsuan Chiu

IPC: H01G4/228 ,  H05K1/18

CPC classification number: H01G4/005 ,  H01G4/228 ,  H01L2224/16225 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10734

Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via. Furthermore, the capacitive module may include a first conductive plane being electrically coupled to a first plane with a first polarity through one of the at least one first conductive via and a second conductive plane being electrically coupled to a second plane with a second polarity, opposite to the first polarity, through one of the at least one second conductive via.

Abstract translation: 提供电容模块。 电容性模块可以包括包括第一电极和第二电极的第一电容器，第一电极和第二电极中的一个耦合到至少一个第一导电通孔，而第一电极和第二电极中的另一个耦合到 至少一个第二导电通孔。 电容性模块还可以包括与第一电容器间隔开的第二电容器，第二电容器包括第三电极和第四电极，第三电极和第四电极中的一个耦合到至少一个第一导电通孔和另一个 第三电极和第四电极中的一个耦合到至少一个第二导电通孔。 此外，电容性模块可以包括第一导电平面，其通过第一导电通孔中的一个与第一极性电耦合到第一平面，第二导电平面电耦合到具有第二极性的第二平面， 通过至少一个第二导电通孔中的一个延伸到第一极性。

公开(公告)号：US20090180225A1

公开(公告)日：2009-07-16

申请号：US12191179

申请日：2008-08-13

Applicant: Chi-Liang Pan ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chen-Hsuan Chiu

Inventor： Chi-Liang Pan ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chen-Hsuan Chiu

IPC: H02H9/00

CPC classification number: H01L23/60 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K1/116 ,  H05K1/167 ,  H05K3/4688 ,  H05K2201/0738 ,  H05K2201/09718 ,  H01L2924/00014

Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.

Abstract translation: 提供ESD保护结构。 衬底包括第一电压可变材料，并具有第一表面，与第一表面基本平行的第二表面和连接第一表面和第二表面的通孔。 第一金属层设置在衬底中用于耦合到接地端子。 当ESD事件发生时，第一电压可变材料处于导通状态，使得通孔与第一金属层电连接以形成放电路径，并且当ESD事件为ESD时，第一电压可变材料处于隔离状态 不存在，使得通孔与第一金属层电隔离。

公开(公告)号：US20090161298A1

公开(公告)日：2009-06-25

申请号：US12050188

申请日：2008-03-18

Applicant: Min-Lin Lee ,  Li-Duan Tsai ,  Shur-Fen Liu ,  Bang-Hao Wu ,  Cheng-Liang Cheng

Inventor： Min-Lin Lee ,  Li-Duan Tsai ,  Shur-Fen Liu ,  Bang-Hao Wu ,  Cheng-Liang Cheng

IPC: H01G9/26 ,  H01G9/15

CPC classification number: H01G9/15 ,  H01G9/0029 ,  H01G9/012 ,  H01L23/642 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/19015 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer.

Abstract translation: 提供了一种混合电容器，其包括基板，至少一个平板电容器和至少一个通孔电容器。 衬底具有通孔，并且板电容器在衬底上。 至少一个通孔电容器和至少一个平板电容器是并联的。 通孔电容器至少包括阳极层，第一电介质层，第一阴极层和第二阴极层。 阳极层设置在至少一个通孔的内表面上，阳极层的表面是多孔结构。 第一介电层设置在阳极层的多孔结构上并被第一阴极层覆盖。 第一阴极层被第二阴极层覆盖。 第二阴极层的导电率大于第一阴极层的导电率。

公开(公告)号：US20090159322A1

公开(公告)日：2009-06-25

申请号：US12046422

申请日：2008-03-11

Applicant: Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

Inventor： Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

IPC: H05K1/18 ,  H01G4/35

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G11/48 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y02E60/13 ,  Y10T29/417 ,  Y10T29/435

Abstract: A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission.

Abstract translation: 提供至少包括基板，阳极层，电介质层，第一阴极层和第二阴极层的通孔电容器。 基板具有多个通孔。 阳极层设置在至少一个通孔的内表面上，阳极层的表面是多孔结构。 电介质层设置在阳极层的多孔结构上。 第一阴极层覆盖电介质层的表面。 第二阴极层覆盖第一阴极层的表面，第二阴极层的导电率大于第一阴极层的导电率。 通孔电容器可用于阻抗控制，因为通孔的阴极层用于信号传输。

公开(公告)号：US20090128993A1

公开(公告)日：2009-05-21

申请号：US12173032

申请日：2008-07-15

Applicant: Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shur-Fen Liu

IPC: H01G4/38

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/38 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/243 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09736 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A multi-tier capacitor structure has at least one multi-tier conductive layer. At least one conductive via passes through the multi-tier conductive layer. When currents flow through the conductive via, different current paths are presented in the conductive via in response to different current frequency; in other words, different inductor is induced. Therefore, a single plate capacitor structure has function of hierarchical decoupling capacitor effect.

Abstract translation: 多层电容器结构具有至少一个多层导电层。 至少一个导电通孔穿过多层导电层。 当电流流过导电通孔时，响应于不同的电流频率，在导电通孔中呈现不同的电流路径; 换句话说，感应不同的电感。 因此，单板电容器结构具有分层去耦电容效应的功能。

公开(公告)号：US20090051469A1

公开(公告)日：2009-02-26

申请号：US12260254

申请日：2008-10-29

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC: H01P1/00

CPC classification number: H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract translation: 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20080266750A1

公开(公告)日：2008-10-30

申请号：US11844280

申请日：2007-08-23

Applicant: Shih-Hsien WU ,  Shinn-Juh LAI ,  Min-Lin LEE ,  Shur-Fen LIU

Inventor： Shih-Hsien WU ,  Shinn-Juh LAI ,  Min-Lin LEE ,  Shur-Fen LIU

IPC: H01G4/06 ,  H01G9/00

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract translation: 引入具有电容的电容器件。 电容器装置包括至少一个电容元件。 所述至少电容元件包括彼此相对的一对第一导电层，至少一个形成在所述第一导电层中的至少一个的表面上的第一电介质层，以及夹在所述第一导电层 。 第一介电层具有第一介电常数，第二介电层具有第二介电常数。 电容器器件的电容取决于第一介电层和第二介电层的介电参数。 介电参数包括第一介电常数和至少一个第一介电层的厚度和第二介电常数和第二介电层的厚度。

公开(公告)号：US20080093113A1

公开(公告)日：2008-04-24

申请号：US11861297

申请日：2007-09-26

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract translation: 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

公开(公告)号：US20070152339A1

公开(公告)日：2007-07-05

申请号：US11708935

申请日：2007-02-20

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC: H01L21/00 ,  H01L21/4763

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

Abstract translation: 提供一种用于在多层电路板中测试包括多个端子的内置组件的方法。 在用于信号传输的多层电路板的顶表面上提供至少一个信号焊盘。 每个信号焊盘电连接到多个端子中的一个。 在多层电路板的顶表面上提供至少一个测试焊盘，并且每个测试焊盘电连接到多个端子之一。 然后，对于电连接到多个端子中的一个的一个信号焊盘和测试焊盘之一进行检测，以便确定从一个信号焊盘延伸通过相同的一个端子的电通路的连接状态 到一个测试垫。

公开(公告)号：US07102876B2

公开(公告)日：2006-09-05

申请号：US11039924

申请日：2005-01-24

Applicant: Min-Lin Lee ,  Chin-Sun Shyu ,  Shur-Fen Liu ,  Jing-Pin Pan ,  Jinn-Shing King

Inventor： Min-Lin Lee ,  Chin-Sun Shyu ,  Shur-Fen Liu ,  Jing-Pin Pan ,  Jinn-Shing King

IPC: H01G4/20

CPC classification number: H01G4/35 ,  H01G4/20 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0355

Abstract: An interleaving striped capacitor substrate structure for pressing-type print circuit boards is disclosed. To meet the high-frequency, high-speed, and high-density requirements in modern electronic systems, the interleaving striped capacitor substrate structure uses several dielectric materials of different dielectric coefficients to make a dielectric layer. One dielectric layer can be stacked on another to form a multi-layered capacitor substrate so that a single capacitor substrate can provide the highest capacitance required for the decoupling capacitor to suppress high-frequency noise signals, and the lower dielectric coefficient substrate required for high-speed signal transmission. This simultaneously achieves the effects of reducing high-frequency transmission time and suppressing high-frequency noise.

Abstract translation: 公开了一种用于按压式印刷电路板的交错条纹电容器基底结构。 为了满足现代电子系统的高频，高速和高密度要求，交错条纹电容器基板结构使用不同介电系数的几种介电材料制成介电层。 一个电介质层可以堆叠在另一个上以形成多层电容器基板，使得单个电容器基板可以提供去耦电容器所需的最高电容以抑制高频噪声信号，并且高电平基板所需的低介电系数基板， 速度信号传输。 这同时实现了降低高频传输时间并抑制高频噪声的效果。