Abstract:
An improved lithographic process for fabricating articles comprising photonic band gap materials with micron-scale periodicities is provided, the process readily capable of being performed by current lithographic processes and equipment. The process involves providing a three-dimensional structure made up of a plurality of stacked layers, where each layer contains a substantially planar lattice of shapes of a first material, typically silicon, with interstices between the shapes. Each shape contacts at least one shape of an adjacent layer, the interstices throughout the plurality of layers are interconnected, and the interstices comprise a second material, e.g., silicon dioxide. Typically, the second material is etched from the interconnected interstices to provide a structure of the first material and air, this structure designed to provide a particular photonic band gap.
Abstract:
Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.
Abstract:
Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.
Abstract:
The present invention provides methods and an apparatus controlling and minimizing process defects in a development process, and modifying line width roughness (LWR) of a photoresist layer after the development process, and maintaining good profile control during subsequent etching processes. In one embodiment, a method for forming features on a substrate includes developing and removing exposed areas in the photosensitive layer disposed on the substrate in the electron processing chamber by predominantly using electrons, removing contaminants from the substrate by predominantly using electrons, and etching the non-photosensitive polymer layer exposed by the developed photosensitive layer in the electron processing chamber by predominantly using electrons.
Abstract:
Methods of and factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A factory includes one or more tool sets for fabricating a thin-film battery.
Abstract:
Embodiments of the invention provide a thin single crystalline silicon film solar cell and methods of forming the same. The method includes forming a thin single crystalline silicon layer on a silicon growth substrate, followed by forming front or rear solar cell structures on and/or in the thin single crystalline silicon film. The method also includes attaching the thin single crystalline silicon film to a mechanical carrier and then separating the growth substrate from the thin single crystalline silicon film along a cleavage plane formed between the growth substrate and the thin single crystalline silicon film. Front or rear solar cell structures are then formed on and/or in the thin single crystalline silicon film opposite the mechanical carrier to complete formation of the solar cell.
Abstract:
Methods and apparatus for forming energy storage devices are provided. In one embodiment a method of producing an energy storage device is provided. The method comprises positioning an anodic current collector into a processing region, depositing one or more three-dimensional electrodes separated by a finite distance on a surface of the anodic current collector such that portions of the surface of the anodic current collector remain exposed, depositing a conformal polymeric layer over the anodic current collector and the one or more three-dimensional electrodes using iCVD techniques comprising flowing a gaseous monomer into the processing region, flowing a gaseous initiator into the processing region through a heated filament to form a reactive gas mixture of the gaseous monomer and the gaseous initiator, wherein the heated filament is heated to a temperature between about 300° C. and about 600° C., and depositing a conformal layer of cathodic material over the conformal polymeric layer.
Abstract:
Solar cells are provided with carbon nanotubes (CNTs) which are used: to define a micron/sub-micron geometry of the solar cells; and/or as charge transporters for efficiently removing charge carriers from the absorber layer to reduce the rate of electron-hole recombination in the absorber layer. A solar cell may comprise: a substrate; a multiplicity of areas of metal catalyst on the surface of the substrate; a multiplicity of carbon nanotube bundles formed on the multiplicity of areas of metal catalyst, each bundle including carbon nanotubes aligned roughly perpendicular to the surface of the substrate; and a photoactive solar cell layer formed over the carbon nanotube bundles and exposed surfaces of the substrate, wherein the photoactive solar cell layer is continuous over the carbon nanotube bundles and the exposed surfaces of the substrate. The photoactive solar cell layer may be comprised of amorphous silicon p/i/n thin films; although, concepts of the present invention are also applicable to solar cells with absorber layers of microcrystalline silicon, SiGe, carbon doped microcrystalline silicon, CIS, CIGS, CISSe and various p-type II-VI binary compounds and ternary and quaternary compounds.
Abstract:
A method of fabricating an energy storage device with a large surface area electrode comprises: providing an electrically conductive substrate; depositing a semiconductor layer on the electrically conductive substrate, the semiconductor layer being a first electrode; anodizing the semiconductor layer, wherein the anodization forms pores in the semiconductor layer, increasing the surface area of the first electrode; after the anodization, providing an electrolyte and a second electrode to form the energy storage device. The substrate may be a continuous film and the electrode of the energy storage device may be fabricated using linear processing tools. The semiconductor may be silicon and the deposition tool may be a thermal spray tool. Furthermore, the semiconductor layer may be amorphous. The energy storage device may be rolled into a cylindrical shape. The energy storage device may be a battery, a capacitor or an ultracapacitor.