公开(公告)号：US08431442B2

公开(公告)日：2013-04-30

申请号：US13253425

申请日：2011-10-05

申请人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

发明人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

摘要翻译： 制造半导体芯片的方法包括提供包括电路区域的半导体衬底，用激光束照射半导体衬底以形成易碎层，以及抛光半导体衬底以将半导体衬底的电路区域彼此分离为半导体芯片 。 在半导体衬底的抛光期间可以完全去除易碎层。

公开(公告)号：US08421244B2

公开(公告)日：2013-04-16

申请号：US12875551

申请日：2010-09-03

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L21/00

CPC分类号： H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

摘要翻译： 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US08129221B2

公开(公告)日：2012-03-06

申请号：US13137260

申请日：2011-08-02

申请人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Tae-Joo Hwang ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

摘要翻译： 示例性实施例涉及半导体封装及其形成方法。 根据示例实施例的半导体封装可以包括印刷电路板（PCB），安装在PCB上的第一半导体芯片和安装在第一半导体芯片上的芯片封装。 芯片封装可以与第一半导体芯片直接接触。

公开(公告)号：US08115324B2

公开(公告)日：2012-02-14

申请号：US12292196

申请日：2008-11-13

申请人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

发明人： Sun-Won Kang ,  Young-Hee Song ,  Tae-Gyeong Chung ,  Nam-Seog Kim ,  Seung-Duk Baek

IPC分类号： H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

摘要翻译： 半导体模块可以包括在电路基板上具有第一裸片的电路基板和在第一裸片上的第二裸片。 第一裸片可以包括在第一裸片的第一周边部分上的至少一个第一数据输入/输出焊盘和第三外围部分上的至少一个第一控制/地址焊盘，第三外围部分与第一外围部分的第一外围部分分离 第一个死亡 第二管芯可以包括在第二外围部分上的至少一个第二数据输入/输出焊盘和第四外围部分上的至少一个第二控制/地址焊盘。 第二模具的第二周边部分在平面图中不与第一模具的第一周边部分重叠。 第二模具的第四周边部分与第一模具的第三周边部分的至少一部分重叠。

公开(公告)号：US20100022051A1

公开(公告)日：2010-01-28

申请号：US12458923

申请日：2009-07-28

申请人： Hae-Jung Yu ,  Eun-Chul Ahn ,  Tae-Gyeong Chung ,  Nam-Seog Kim

发明人： Hae-Jung Yu ,  Eun-Chul Ahn ,  Tae-Gyeong Chung ,  Nam-Seog Kim

IPC分类号： H01L21/50 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24226 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2224/82

摘要： A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.

摘要翻译： 提供一种制造具有堆叠芯片的电子设备的方法。 该方法包括形成沿行方向布置的多个芯片和沿列方向布置的至少一个芯片。 在芯片之间形成模制层。 在沿行方向布置的芯片之间的成型层中形成凹槽。 在具有凹槽的基板上形成导电互连。 衬底沿着奇数或偶数编号的一个沟槽被锯切，以分离成多个单位衬底。 分离的单元基板中的至少一个沿着凹槽的未开槽的凹槽折叠。

公开(公告)号：US20080173999A1

公开(公告)日：2008-07-24

申请号：US11969037

申请日：2008-01-03

申请人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Tae-Gyeong CHUNG ,  Nam-Seog KIM ,  Seung-Kwan RYU

发明人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Tae-Gyeong CHUNG ,  Nam-Seog KIM ,  Seung-Kwan RYU

IPC分类号： H01L23/538

CPC分类号： H01L24/19 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/18 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A stack package and a method of manufacturing the same are provided. The stack package includes one or more interposers in which a semiconductor chip having a bonding pad are inserted, an interconnection terminal groove is formed due to a difference of the areas between the semiconductor chip and a cavity into which the semiconductor chip is inserted, and an interconnection terminal connected to the bonding pad is formed in the interconnection terminal groove. In the stack package, the interposers are stacked with one another and the interconnection terminals are connected to one another such that one or more semiconductor chips are stacked and electrically connected.

摘要翻译： 提供了堆叠包及其制造方法。 堆叠封装包括一个或多个插入件，其中插入具有焊盘的半导体芯片，由于半导体芯片和插入半导体芯片的空腔之间的区域的差异而形成互连端子槽，并且 连接到接合焊盘的互连端子形成在互连端子槽中。 在堆叠封装中，插入物彼此堆叠，并且互连端子彼此连接，使得一个或多个半导体芯片被堆叠并电连接。

公开(公告)号：US07335592B2

公开(公告)日：2008-02-26

申请号：US11253755

申请日：2005-10-20

申请人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

发明人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124

摘要： A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

摘要翻译： 半导体芯片封装包括半导体芯片，该半导体芯片具有从活性第一表面延伸到非活性第二表面的通孔。 第一导电焊盘至少部分地围绕半导体芯片的有源第一表面上的通孔。 封装还包括具有附接到半导体芯片的非活性第二表面的第一表面的印刷电路板和与半导体芯片的通孔对准的第二导电焊盘。 导电材料填充通孔并接触第一和第二导电焊盘。

公开(公告)号：US06982487B2

公开(公告)日：2006-01-03

申请号：US10665630

申请日：2003-09-22

申请人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

发明人： Hyeong-Seob Kim ,  Tae-Gyeong Chung

IPC分类号： H01L23/48

CPC分类号： H01L24/10 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124

摘要： A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

摘要翻译： 半导体芯片封装包括半导体芯片，该半导体芯片具有从活性第一表面延伸到非活性第二表面的通孔。 第一导电焊盘至少部分地围绕半导体芯片的有源第一表面上的通孔。 封装还包括具有附接到半导体芯片的非活性第二表面的第一表面的印刷电路板和与半导体芯片的通孔对准的第二导电焊盘。 导电材料填充通孔并接触第一和第二导电焊盘。

公开(公告)号：US20050205975A1

公开(公告)日：2005-09-22

申请号：US11077235

申请日：2005-03-11

申请人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

发明人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

IPC分类号： H01L25/18 ,  H01L21/301 ,  H01L21/50 ,  H01L21/60 ,  H01L21/78 ,  H01L21/98 ,  H01L23/02 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06

CPC分类号： H01L24/32 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2224/85186 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.

摘要翻译： 提供了具有包括一个或多个凹陷或凹入周边区域的阶梯状或改进的周边或边缘轮廓的各种非矩形IC芯片，用于结合到改进的封装结构，单个芯片封装和多芯片组件中，堆叠和/或平面 。 在平面构造中，可以与另一适当尺寸的IC芯片配合使用凹陷区域，以增加所得器件的封装密度。 类似地，在堆叠构造中，凹陷区域可以用于提供对下部芯片的接合焊盘的访问，从而减少对间隔件或外围变薄技术的需要，从而提高所得组件的强度和/或降低总体高度 堆叠结构。

公开(公告)号：US06857470B2

公开(公告)日：2005-02-22

申请号：US10719670

申请日：2003-11-20

申请人： Hee-Jin Park ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

发明人： Hee-Jin Park ,  Tae-Gyeong Chung ,  Eun-Chul Ahn

IPC分类号： H01L23/34 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L21/50 ,  F28F7/00

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L23/36 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/0651 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48471 ,  H01L2224/45099 ,  H01L2224/4554

摘要： The present invention provides a stacked chip package having at least one heat transfer wire. The heat transfer wire is disposed between the stacked chips and at least one end of each transfer wire is connected to a dummy pad provided on the board. Therefore, the heat generated by the chips and trapped between the chips can be effectively dissipated. The heat transfer wires can be formed on the uppermost chip of the stacked chips to enhance the heat dissipation. In addition, by controlling the number or the size of the heat transfer wire, the thermal characteristics of the stacked chip package can be modified.

摘要翻译： 本发明提供一种具有至少一个传热线的堆叠式芯片封装。 传热线设置在堆叠的芯片之间，并且每个传输线的至少一端连接到设置在板上的虚拟焊盘。 因此，可以有效地消散由芯片产生的并被捕获在芯片之间的热量。 传热线可以形成在堆叠芯片的最上面的芯片上，以增强散热。 此外，通过控制传热丝的数量或尺寸，可以改变堆叠的芯片封装的热特性。