公开(公告)号：US20080173999A1

公开(公告)日：2008-07-24

申请号：US11969037

申请日：2008-01-03

申请人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Tae-Gyeong CHUNG ,  Nam-Seog KIM ,  Seung-Kwan RYU

发明人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Tae-Gyeong CHUNG ,  Nam-Seog KIM ,  Seung-Kwan RYU

IPC分类号： H01L23/538

CPC分类号： H01L24/19 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/18 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/30105 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A stack package and a method of manufacturing the same are provided. The stack package includes one or more interposers in which a semiconductor chip having a bonding pad are inserted, an interconnection terminal groove is formed due to a difference of the areas between the semiconductor chip and a cavity into which the semiconductor chip is inserted, and an interconnection terminal connected to the bonding pad is formed in the interconnection terminal groove. In the stack package, the interposers are stacked with one another and the interconnection terminals are connected to one another such that one or more semiconductor chips are stacked and electrically connected.

摘要翻译： 提供了堆叠包及其制造方法。 堆叠封装包括一个或多个插入件，其中插入具有焊盘的半导体芯片，由于半导体芯片和插入半导体芯片的空腔之间的区域的差异而形成互连端子槽，并且 连接到接合焊盘的互连端子形成在互连端子槽中。 在堆叠封装中，插入物彼此堆叠，并且互连端子彼此连接，使得一个或多个半导体芯片被堆叠并电连接。

公开(公告)号：US20080290492A1

公开(公告)日：2008-11-27

申请号：US12123367

申请日：2008-05-19

申请人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Nam-Seog KIM ,  Sun-Won KANG

发明人： Hyun-Soo CHUNG ,  Dong-Hyeon JANG ,  Nam-Seog KIM ,  Sun-Won KANG

IPC分类号： H01L23/488

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00

摘要： Provided is a semiconductor package with enhanced joint reliability and methods of fabricating the same. The method includes: forming package units including a semiconductor chip interposed between a bottom layer and a top layer; and sequentially stacking the package units on a substrate. The bottom layer and the top layer are formed of a material having a lower modulus than the semiconductor chip. The semiconductor package includes: at least one package unit disposed on a substrate, the package unit including a semiconductor chip having a pad, a bottom layer and a top layer substantially surrounding the semiconductor chip, and a redistribution structure overlying the top layer. The redistribution structure is electrically connected to the pad.

摘要翻译： 提供了具有增强的接头可靠性的半导体封装以及其制造方法。 该方法包括：形成包括插入在底层和顶层之间的半导体芯片的封装单元; 并且将所述封装单元依次堆叠在基板上。 底层和顶层由具有比半导体芯片低的模量的材料形成。 所述半导体封装包括：设置在基板上的至少一个封装单元，所述封装单元包括具有衬垫，底层和基本上围绕所述半导体芯片的顶层的半导体芯片以及覆盖所述顶层的再分布结构。 再分配结构电连接到焊盘。

公开(公告)号：US20080014735A1

公开(公告)日：2008-01-17

申请号：US11775120

申请日：2007-07-09

申请人： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

发明人： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

摘要： Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

摘要翻译： 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20090206464A1

公开(公告)日：2009-08-20

申请号：US12432003

申请日：2009-04-29

申请人： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

发明人： Hyun-Soo CHUNG ,  Seung-Kwan RYU ,  Ju-Il CHOI ,  Dong-Ho LEE ,  Seong-Deok HWANG

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

摘要： Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

摘要翻译： 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20070164431A1

公开(公告)日：2007-07-19

申请号：US11549933

申请日：2006-10-16

申请人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

发明人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/5222 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

摘要： A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

摘要翻译： 提供能够降低重新布线和晶片的金属布线之间的寄生电容的晶片级芯片级封装及其制造方法。 晶片级芯片级封装的实施例包括具有多个接合焊盘的晶片和形成在晶片上的绝缘部件，使得焊盘露出。 在与暴露的接合焊盘接触的绝缘构件上进一步形成再路由，并且外部连接端子电连接到重新布线的一部分。 这里，与重新路由重叠的绝缘构件设置有空气被捕获的多个空间。

公开(公告)号：US20090184411A1

公开(公告)日：2009-07-23

申请号：US12353501

申请日：2009-01-14

申请人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

发明人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC分类号： H01L23/48

CPC分类号： H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20120129334A1

公开(公告)日：2012-05-24

申请号：US13365378

申请日：2012-02-03

申请人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

发明人： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC分类号： H01L21/768

CPC分类号： H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20090302418A1

公开(公告)日：2009-12-10

申请号：US12478365

申请日：2009-06-04

申请人： Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Hyeon JANG ,  Eun-Chul AHN ,  Kun-Gu LEE ,  Chang-Woo SHIN

发明人： Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Dong-Hyeon JANG ,  Eun-Chul AHN ,  Kun-Gu LEE ,  Chang-Woo SHIN

IPC分类号： H01L23/525

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse.

摘要翻译： 提供半导体器件的熔丝结构。 熔丝结构可以包括绝缘层图案结构，熔丝和保护层图案。 绝缘层图案结构可以形成在基板上。 绝缘层图案结构可以具有开口。 保险丝可以形成在开口中。 保护层图案可以形成在绝缘层图案结构的开口中以覆盖保险丝。

公开(公告)号：US20090008790A1

公开(公告)日：2009-01-08

申请号：US12132925

申请日：2008-06-04

申请人： Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

发明人： Ho-Jin LEE ,  Nam-Seog KIM ,  Yong-Chai KWON ,  Hyun-Soo CHUNG ,  In-Young LEE ,  Son-Kwan HWANG

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

摘要： A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

摘要翻译： 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US20080128905A1

公开(公告)日：2008-06-05

申请号：US11950251

申请日：2007-12-04

申请人： In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

发明人： In-Young LEE ,  Dong-Ho LEE ,  Nam-Seog KIM ,  Hyun-Soo CHUNG ,  Ho-Jin LEE ,  Myeong-Soo PARK

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

摘要翻译： 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。