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    MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE
    11.
    发明申请
    MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE 有权
    存储器件中的多级程序验证

    公开(公告)号：US20120269004A1

    公开(公告)日：2012-10-25

    申请号：US13537150

    申请日：2012-06-29

    Applicant: Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

    Inventor： Taehoon Kim ,  Deping He ,  Jeffrey Alan Kessenich

    IPC: G11C16/06

    CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

    Abstract translation: 一系列编程脉冲被施加到要编程的存储器单元。 在每个编程脉冲之后，在初始程序验证电压下将程序验证脉冲施加到存储单元。 初始程序验证电压是通过快速充电损耗电压增加的验证电压。 在编程脉冲达到某个参考电压或编程脉冲数达到脉冲计数阈值之后，从初始编程验证电压中减去快速充电损耗电压。

    Printed circuit board and method of manufacturing the same
    16.
    发明申请
    Printed circuit board and method of manufacturing the same 失效
    印刷电路板及其制造方法

    公开(公告)号：US20070141310A1

    公开(公告)日：2007-06-21

    申请号：US11585276

    申请日：2006-10-24

    Applicant: Jong Seok Song ,  Taehoon Kim

    Inventor： Jong Seok Song ,  Taehoon Kim

    IPC: B05D5/12 ,  B32B3/00

    CPC classification number: H05K1/036 ,  B32B3/266 ,  B32B27/08 ,  B32B27/16 ,  B32B27/28 ,  B32B27/281 ,  B32B27/304 ,  B32B27/322 ,  B32B27/38 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2255/26 ,  B32B2255/28 ,  B32B2307/728 ,  B32B2457/08 ,  C08J7/045 ,  H05K1/034 ,  H05K3/108 ,  H05K3/381 ,  H05K3/426 ,  H05K2201/015 ,  H05K2203/092 ,  Y10T428/24917

    Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.

    Abstract translation: 公开了一种印刷电路板及其制造方法，其中在树脂基板上形成氟树脂涂层，然后使用包括离子束表面处理和真空沉积的干法形成铜层，而不是形成铜层 常规湿法包括表面粗糙化和无电镀铜。 根据本发明，可以在不改变其表面粗糙度的情况下增加基板材料的界面粘合性，从而实现高可靠性的精细电路。 同样，由于氟树脂层的形成，可以获得低介电常数和低损耗系数。 此外，用干法代替湿法，由此可以以环境友好的方式形成铜镀层。

    STORAGE DEVICE AND RELIABILITY VERIFICATION METHOD
    17.
    发明申请
    STORAGE DEVICE AND RELIABILITY VERIFICATION METHOD 审中-公开
    存储设备和可靠性验证方法

    公开(公告)号：US20160307635A1

    公开(公告)日：2016-10-20

    申请号：US15193134

    申请日：2016-06-27

    Applicant: KYUNGRYUN KIM ,  TAEHOON KIM ,  SANGKWON MOON

    Inventor： KYUNGRYUN KIM ,  TAEHOON KIM ,  SANGKWON MOON

    IPC: G11C16/28 ,  G11C16/34

    CPC classification number: G11C16/28 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3495

    Abstract: A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining whether a read count for a designated unit within the nonvolatile memory device exceeds a count value limit, and upon determining that the read count exceeds the count value limit, executing the reliability verification operation directed to the designated unit, wherein the count value limit is based on at least one of read count information, page bitmap information and environment information stored in the storage device.

    Abstract translation: 一种控制在包括非易失性存储装置的存储装置中执行可靠性验证操作的方法包括： 确定非易失性存储装置内的指定单元的读取计数是否超过计数值限制，并且在确定读取计数超过计数值限制时，执行针对指定单元的可靠性验证操作，其中计数值限制为 基于存储在存储装置中的读取计数信息，页面位图信息和环境信息中的至少一个。

    Method for manufacturing model
    18.
    发明授权
    Method for manufacturing model 有权
    制造模式的方法

    公开(公告)号：US09346136B2

    公开(公告)日：2016-05-24

    申请号：US14118921

    申请日：2011-06-13

    Applicant: Taehoon Kim

    Inventor： Taehoon Kim

    IPC: B23P19/04 ,  G09B19/10 ,  A63H9/00 ,  A63H33/42 ,  A63F9/12 ,  B44C3/12 ,  B44C3/02

    CPC classification number: B23P19/04 ,  A63F9/1288 ,  A63F2009/1292 ,  A63F2009/1296 ,  A63H9/00 ,  A63H33/42 ,  B44C3/025 ,  B44C3/12 ,  G09B19/10 ,  Y10T29/49789 ,  Y10T29/49798 ,  Y10T29/49826 ,  Y10T29/49885

    Abstract: A method for manufacturing a model is disclosed. The disclosed method for manufacturing the model comprises the steps of: a) preparing a plurality of pieces having contours in the shape of cross-sections of an object from specific distances away from a random axis direction; and b) assembling the plurality of pieces according to an integration process of connecting surfaces of adjacent pieces from the plurality of pieces and fixing same to each other so as to form the model which corresponds to the shape of the object.

    Abstract translation: 公开了一种用于制造模型的方法。 所公开的用于制造模型的方法包括以下步骤：a）准备多个具有距离随机轴方向特定距离的物体的横截面形状的轮廓的部件; 以及b）根据从所述多个片的相邻片的连接表面的整合过程将所述多个片组合，并将它们彼此固定，以形成与所述物体的形状对应的模型。

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