公开(公告)号：US11121031B2

公开(公告)日：2021-09-14

申请号：US16668570

申请日：2019-10-30

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/02

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US20210210436A1

公开(公告)日：2021-07-08

申请号：US17140964

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/66

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US11038077B2

公开(公告)日：2021-06-15

申请号：US16291637

申请日：2019-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Po-Han Lee ,  Chien-Min Lin ,  Yi-Rong Ho

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/028

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

公开(公告)号：US20210082841A1

公开(公告)日：2021-03-18

申请号：US17023199

申请日：2020-09-16

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Jiun-Yen LAI ,  Ming-Chung CHUNG ,  Wei-Luen SUEN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

公开(公告)号：US10388541B2

公开(公告)日：2019-08-20

申请号：US15098278

申请日：2016-04-13

Applicant: XINTEC INC.

Inventor： Yu-Tung Chen ,  Quan-Qun Su ,  Chuan-Jin Shiu ,  Chien-Hui Chen ,  Hsiao-Lan Yeh ,  Yen-Shih Ho

IPC: H01L21/56 ,  H01L21/687 ,  H01L21/67 ,  H01L23/31 ,  H01L21/768 ,  H01L21/02 ,  H01L23/00

Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.

公开(公告)号：US10347616B2

公开(公告)日：2019-07-09

申请号：US15590302

申请日：2017-05-09

Applicant: XINTEC INC.

Inventor： Hsin Kuan ,  Chin-Ching Huang ,  Chia-Ming Cheng

IPC: H01L25/16 ,  H01L31/0203 ,  H01L23/538 ,  H01L23/00 ,  H01L27/146 ,  H01L23/051

Abstract: A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.

公开(公告)号：US20190140012A1

公开(公告)日：2019-05-09

申请号：US16178483

申请日：2018-11-01

Applicant: XINTEC INC.

Inventor： Hsin KUAN ,  Shih-Kuang CHEN ,  Chin-Ching HUANG ,  Chia-Ming CHENG

IPC: H01L27/146 ,  H01L23/00 ,  H01L21/56

Abstract: A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening.

公开(公告)号：US09875924B2

公开(公告)日：2018-01-23

申请号：US15053521

申请日：2016-02-25

Applicant: XINTEC INC.

Inventor： Tsou-Tso Tsai ,  Kuo-Ching Wu ,  Tzung-Heng Tsai

IPC: B05C13/02 ,  B05C11/02 ,  H01L21/683 ,  H01L21/67

CPC classification number: H01L21/6838 ,  H01L21/6715

Abstract: A spray coater is used to spray a photoresist on a front surface of a wafer. The spray coater includes a vacuum chuck, a flow guiding ring, and a positioning ring. The vacuum chuck has a top surface and a side surface adjacent to the top surface. The wafer is located on the top surface and protrudes from the top surface of the vacuum chuck. The flow guiding ring is disposed around the vacuum chuck and has a groove. The wafer protruding from the top surface covers the flow guiding ring, and an opening of the groove faces a back surface of the wafer opposite to the front surface. The positioning ring is disposed around the flow guiding ring, such that the flow guiding ring is between the positioning ring and the side surface of the vacuum chuck.

公开(公告)号：US09761555B2

公开(公告)日：2017-09-12

申请号：US14604525

申请日：2015-01-23

Applicant: XINTEC INC.

Inventor： Jiun-Yen Lai ,  Yu-Wen Hu ,  Bai-Yao Lou ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Hsin Kuan

IPC: H01L31/00 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

公开(公告)号：US09761510B2

公开(公告)日：2017-09-12

申请号：US14706896

申请日：2015-05-07

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/488 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/488 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/12105 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48464 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/10253 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2924/00

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.