公开(公告)号：US20190181246A1

公开(公告)日：2019-06-13

申请号：US16277634

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Ying ZHANG ,  Qingjun ZHOU ,  Yung-chen LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762

Abstract: Methods for forming semiconductor devices, such as FinFETs, are provided. In an embodiment, a fin structure processing method includes removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, wherein the fins are adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, wherein the etching operation is performed in the same chamber as the deposition operation.

公开(公告)号：US20180277649A1

公开(公告)日：2018-09-27

申请号：US15933072

申请日：2018-03-22

Applicant: Applied Materials, Inc.

Inventor： Zhiyuan YE ,  Xinyu BAO ,  Chun YAN ,  Hua CHUNG ,  Schubert S. CHU ,  Satheesh KUPPURAO

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/02546 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/67167 ,  H01L21/823431 ,  H01L21/8252

Abstract: Methods of sub-10 nm fin formation are disclosed. One method includes patterning a first dielectric layer on a substrate to form one or more projections and a first plurality of spaces, and depositing a first plurality of columns in the first plurality of spaces. The first plurality of columns are separated by a second plurality of spaces. The method also includes depositing a second dielectric layer in the second plurality of spaces to form a plurality of dummy fins, removing the first plurality of columns to form a third plurality of spaces, depositing a second plurality of columns in the third plurality of spaces, removing the one or more projections and the plurality of dummy fins to form a fourth plurality of spaces, and depositing a plurality of fins in the fourth plurality of spaces. The plurality of fins have a width between 5-10 nm.

公开(公告)号：US20180261454A9

公开(公告)日：2018-09-13

申请号：US15194361

申请日：2016-06-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Zhiyuan YE ,  Jean-Baptiste PIN ,  Errol SANCHEZ ,  Franck BASSANI ,  Thierry BARON ,  Yann BOGUMILOWICZ ,  Jean-Michel HARTMANN

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/201 ,  H01L29/06

Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a plane and a plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the plane in the direction of the plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.

公开(公告)号：US20180174825A1

公开(公告)日：2018-06-21

申请号：US15890117

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO ,  Melitta Manyin HON ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L21/02057 ,  H01L29/66636 ,  H01L29/66795

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US20180033659A1

公开(公告)日：2018-02-01

申请号：US15414326

申请日：2017-01-24

Applicant: Applied Materials, Inc.

Inventor： Chun YAN ,  Xinyu BAO

IPC: H01L21/67 ,  B08B15/00 ,  C30B33/00 ,  C30B25/12 ,  C30B25/08 ,  C30B25/14

CPC classification number: H01L21/67201 ,  B08B15/00 ,  B08B15/02 ,  B08B2215/003 ,  C23C16/45508 ,  C23C16/4551 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45576 ,  C23C16/4558 ,  C30B25/08 ,  C30B25/12 ,  C30B25/14 ,  C30B33/00 ,  H01L21/67017

Abstract: Embodiments disclosed herein generally relate to a system, method, and apparatus for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a III-V epitaxial growth process or an etch clean process, and prior to additional processing. An oxygen containing gas is flowed to a substrate in a load lock chamber, and subsequently a non-reactive gas is flowed to the substrate in the load lock chamber. As such, hazardous gases and outgassing residuals are decreased and/or removed from the substrate such that further processing may be performed.

公开(公告)号：US20160362813A1

公开(公告)日：2016-12-15

申请号：US15156371

申请日：2016-05-17

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Shu-Kwan LAU ,  Errol Antonio C. SANCHEZ

IPC: C30B25/14 ,  C30B25/10 ,  H01L21/02 ,  C30B29/16 ,  C30B29/48 ,  C23C16/455 ,  C30B29/40

CPC classification number: C30B25/14 ,  C23C16/45508 ,  C23C16/45574 ,  C30B25/105 ,  C30B29/06 ,  C30B29/08 ,  C30B29/16 ,  C30B29/40 ,  C30B29/48 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/0262 ,  H01L21/02636

Abstract: A processing chamber with a top, a bottom, and a sidewall coupled together to define an enclosure, a substrate support having a substrate supporting surface, an energy source coupled to the top or the bottom, and a gas injector liner disposed at the sidewall. The gas injector liner comprises a first plurality of gas outlets disposed at a first height, wherein one or more of the first plurality of gas outlets are oriented upwardly or downwardly, a second plurality of gas outlets disposed at a second height shorter than the first height, wherein one or more of the second plurality of gas outlets are oriented upwardly or downwardly, and a third plurality of gas outlets disposed at a third height shorter than the second height, wherein one or more of the third plurality of gas outlets are oriented upwardly or downwardly with respect to the substrate supporting surface.

Abstract translation: 一种具有顶部，底部和侧壁的处理室，其联接在一起以限定外壳，具有基板支撑表面的基板支撑件，联接到顶部或底部的能量源以及设置在侧壁处的气体注入器衬套。 气体注入器衬套包括设置在第一高度处的第一多个气体出口，其中第一多个气体出口中的一个或多个朝上或向下取向;第二多个气体出口，其设置在比第一高度短的第二高度处 ，其中所述第二多个气体出口中的一个或多个向上或向下取向，以及设置在比所述第二高度短的第三高度处的第三多个气体出口，其中所述第三多个气体出口中的一个或多个朝向上 或相对于基板支撑表面向下。

公开(公告)号：US20140329376A1

公开(公告)日：2014-11-06

申请号：US14262400

申请日：2014-04-25

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C. SANCHEZ ,  Xinyu BAO ,  Wonseok LEE ,  David Keith CARLSON ,  Zhiyuan YE

IPC: H01L21/02

CPC classification number: H01L21/02546 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/762

Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A surface may be formed on a substrate and a Group III-V material may be grown from the surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.

Abstract translation: 本文描述的实施例通常涉及在衬底上制造包含III-V族元素的器件结构的方法。 可以在衬底上形成A 111表面，并且可以从III族表面生长III-V族材料，以在介电层之间隔离的沟槽中形成III-V族器件结构。 可以修剪设备结构的最终关键尺寸以实现适当尺寸的节点结构。

公开(公告)号：US20180076065A1

公开(公告)日：2018-03-15

申请号：US15418506

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/67 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/285 ,  H01J37/32 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  B08B7/00

CPC classification number: H01L21/67207 ,  B08B7/0035 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01J37/32458 ,  H01J37/32899 ,  H01J2237/334 ,  H01L21/02046 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/3065 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67201 ,  H01L29/66636 ,  H01L29/66795

Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to an integrated system for processing N-type metal-oxide semiconductor (NMOS) devices. In one implementation, a cluster tool for processing a substrate is provided. The cluster tool includes a pre-clean chamber, an etch chamber, one or more pass through chambers, one or more outgassing chambers, a first transfer chamber, a second transfer chamber, and one or more process chambers. The pre-clean chamber and the etch chamber are coupled to a first transfer chamber. The one or more pass through chambers are coupled to and disposed between the first transfer chamber and the second transfer chamber. The one or more outgassing chambers are coupled to the second transfer chamber. The one or more process chambers are coupled to the second transfer chamber.

公开(公告)号：US20180033621A1

公开(公告)日：2018-02-01

申请号：US15417556

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Chun YAN ,  Errol Antonio C. SANCHEZ

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02513 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/31111

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes applying a passivating agent containing antimony to portions of a silicon substrate exposed through trenches formed in a dielectric layer on the silicon substrate, while applying the passivating agent containing antimony, exposing the silicon substrate to a group IV-containing precursor to form an epitaxial layer having a V-shaped structure having an exposed (111) plane at a bottom of the trenches, and forming a semiconductor layer on the epitaxial layer.

公开(公告)号：US20160343811A1

公开(公告)日：2016-11-24

申请号：US15185749

申请日：2016-06-17

Applicant: Applied Materials, Inc.

Inventor： Xinyu BAO ,  Errol Antonio C. SANCHEZ ,  David K. CARLSON ,  Zhiyuan YE

IPC: H01L29/205 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02694 ,  H01L29/267 ,  Y10T117/1008

Abstract: A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.