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    Method of making an interposer
    11.
    发明授权
    Method of making an interposer 有权
    制作插件的方法

    公开(公告)号：US07511518B2

    公开(公告)日：2009-03-31

    申请号：US11902976

    申请日：2007-09-27

    Applicant: Frank D. Egitto ,  How T. Lin

    Inventor： Frank D. Egitto ,  How T. Lin

    IPC: G01R31/02

    CPC classification number: H05K3/4007 ,  G01R1/06711 ,  G01R1/0735 ,  H05K1/0393 ,  H05K3/365 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

    Abstract: A method of making an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers as part of this method. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.

    Abstract translation: 一种制造其中至少两个电介质层彼此结合以夹在其间的多个导体的插入件的方法。 这些导体各自电耦合相应的一对相对的电触点，其形成在也作为该方法的一部分的电介质层内形成的开口内并从其中突出。 所得到的内插器非常适合用作测试装置的一部分，以将半导体芯片的高密度图案的焊球接触件与装置的印刷电路板上的较小致密的触点阵列相互连接。

    Method of forming multilayer capacitors in a printed circuit substrate
    13.
    发明授权
    Method of forming multilayer capacitors in a printed circuit substrate 有权
    在印刷电路基板中形成多层电容器的方法

    公开(公告)号：US08501575B2

    公开(公告)日：2013-08-06

    申请号：US12909983

    申请日：2010-10-22

    Applicant: Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    Inventor： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC: H01G4/00

    CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

    Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

    Abstract translation: 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

    METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE
    14.
    发明申请
    METHOD OF FORMING MULTILAYER CAPACITORS IN A PRINTED CIRCUIT SUBSTRATE 有权
    在印刷电路基板中形成多层电容器的方法

    公开(公告)号：US20120223047A1

    公开(公告)日：2012-09-06

    申请号：US12909983

    申请日：2010-10-22

    Applicant: Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    Inventor： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC: H01G4/002 ,  G03F7/30 ,  G03F7/20

    CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

    Abstract: Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

    Abstract translation: 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

    Method of making a circuitized substrate having at least one capacitor therein
    15.
    发明申请
    Method of making a circuitized substrate having at least one capacitor therein 审中-公开
    制造其中具有至少一个电容器的电路化基板的方法

    公开(公告)号：US20080248596A1

    公开(公告)日：2008-10-09

    申请号：US11878673

    申请日：2007-07-26

    Applicant: Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    Inventor： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

    IPC: H01L21/77

    CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

    Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.

    Abstract translation: 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。 在另一个实施例中，可以在沉积在电介质层上的金属层内形成至少两个间隔开的导体，这些导体在其间限定通道。 然后可以在通道内沉积（例如，使用层压）的电容电介质材料。

    Multi-functional fiber optic coupler
    17.
    发明授权
    Multi-functional fiber optic coupler 有权

    公开(公告)号：US06635866B2

    公开(公告)日：2003-10-21

    申请号：US09838645

    申请日：2001-04-19

    Applicant: Benson Chan ,  Richard R. Hall ,  How T. Lin ,  John H. Sherman

    Inventor： Benson Chan ,  Richard R. Hall ,  How T. Lin ,  John H. Sherman

    IPC: H01J502

    CPC classification number: G02B6/4292 ,  G02B6/3885 ,  G02B6/3897 ,  G02B6/4232 ,  G02B6/4249

    Abstract: An optical coupler that provides for the direct mounting of integrated circuit(s). The coupler includes a two-part housing with grooves for accommodating optical fibers that are held in place when the two parts are put together. Circuitry is formed on the housing and solder balls, when heated to a liquid state and cooled (reflowed), are used to attach integrated circuit(s) onto the housing. At least one of these integrated circuit(s) is an optical die that is positioned in close proximity to the optical fibers to provide for the receipt and/or transmission of optical signals. The reflowing of the solder balls forms an electrical connection between the circuitry on the housing and the integrated circuit(s) and provides for alignment of these components. The housing is attached to a circuitized substrate using reflowed solder balls or wirebonds.

    Method of making circuitized substrate with internal optical pathway using photolithography
    19.
    发明申请
    Method of making circuitized substrate with internal optical pathway using photolithography 失效
    使用光刻法制造具有内部光学路径的电路化衬底的方法

    公开(公告)号：US20090093073A1

    公开(公告)日：2009-04-09

    申请号：US11907004

    申请日：2007-10-09

    Applicant: Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    Inventor： Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    IPC: H01L21/77

    CPC classification number: G02B6/43 ,  G02B6/132 ,  G02B6/136 ,  H05K1/0274

    Abstract: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum. The formed substrate is capable of being both optically and electrically coupled to one or more other substrates possessing similar capabilities, thereby forming an electro-optical assembly of such substrates.

    Abstract translation: 一种制造电路化衬底（例如，PCB）的方法，其包括至少一个可能的几个内部光学路径作为其一部分，使得所得到的衬底将能够传输和/或接收电信号和光信号。 该方法包括在光学核心的一侧和相邻的直立构件之间形成至少一个开口，使得开口由至少一个角形侧壁限定。 通过光学芯材料（或从上方进入芯体）的光从该角形侧壁反射。 因此，开口内的介质（例如空气）由于其相对于相邻的光学芯材料的反射率而与反射介质一样起作用。 该方法利用了常规PCB制造中使用的许多工艺，从而将成本降至最低。 所形成的基底能够光学和电耦合到具有相似能力的一个或多个其它基底，从而形成这种基底的电光学组件。

    Method of making circuitized substrate with internal optical pathway
    20.
    发明申请
    Method of making circuitized substrate with internal optical pathway 有权
    制造具有内部光通路的电路化基板的方法

    公开(公告)号：US20090092353A1

    公开(公告)日：2009-04-09

    申请号：US11907006

    申请日：2007-10-09

    Applicant: Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    Inventor： Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

    IPC: G02B6/122

    CPC classification number: G02B6/1221 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4246 ,  H05K1/0274

    Abstract: A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided.

    Abstract translation: 包括作为其一部分的内部光学路径的电路化衬底（例如，PCB），使得衬底能够传输和/或接收电信号和光信号。 衬底包括在一个包覆层上的角反射器，使得穿过光学核心的光信号将撞击角形反射器的成角度的反射表面，并通过开口（包括其中具有光学透明材料的一个）反射，例如 涉及另外还具有至少一个内部光学路径作为其一部分的第二电路化基板，从而光学地连接两个基板。 还提供了制造基板的方法。

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