公开(公告)号：US20180174895A1

公开(公告)日：2018-06-21

申请号：US15379707

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Guillaume BOUCHE

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.

公开(公告)号：US20170250080A1

公开(公告)日：2017-08-31

申请号：US15053818

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Jason Eugene STEPHENS

IPC: H01L21/033 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/0337 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228

Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

公开(公告)号：US20160322298A1

公开(公告)日：2016-11-03

申请号：US15207652

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Andy WEI ,  Sudharshanan RAGHUNATHAN

IPC: H01L23/528 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

Abstract translation: 在Mx线之前光刻地切割Mx线的方法通过图案化光刻定义，并且提供所得到的2DSAV器件。 实施例包括在SiO 2层上形成a-Si虚拟金属层; 在所述a-Si虚拟金属层上形成第一软掩模堆叠; 将通过第一软掩模堆叠的多个通孔图形化成SiO 2层; 移除第一软掩模层; 在a-Si虚拟金属层上形成第一和第二蚀刻停止层，形成在多个通孔中的第一蚀刻停止层; 在第二蚀刻停止层上形成a-Si心轴; 在每个a-Si心轴的相对侧上形成氧化物间隔物; 去除a-Si心轴; 在氧化物间隔物下面的a-Si虚拟金属层中形成a-Si虚拟金属线; 并在a-Si虚拟金属线之间形成SiOC层。

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.

公开(公告)号：US20180337037A1

公开(公告)日：2018-11-22

申请号：US15598393

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume BOUCHE ,  Vimal KAMINENI

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/02175 ,  H01L21/02205 ,  H01L21/28026 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/785

Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20180174894A1

公开(公告)日：2018-06-21

申请号：US15379605

申请日：2016-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume BOUCHE ,  Nicholas Vincent LICAUSI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/302 ,  H01L21/308 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.

公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20160155800A1

公开(公告)日：2016-06-02

申请号：US14988050

申请日：2016-01-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Guillaume BOUCHE ,  Gabriel Padron WELLS

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L21/308 ,  H01L29/16

CPC classification number: H01L29/0673 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).

Abstract translation: 提出了用于促进制造堆叠的纳米线，场效应晶体管的方法。 所述方法包括：在栅极结构上形成切割掩模间隔物，栅极结构设置在衬底结构上方的多层上方，栅极结构包括沿其侧壁的侧壁间隔物和覆盖侧壁间隔物的切割掩模间隔物; 通过使用切割掩模间隔物和栅极结构作为掩模切割多个层来限定堆叠结构，并且部分地选择性地蚀刻多个层的至少一个层以部分地掩盖掩模，其中至少一个其它层 通过选择性蚀刻，多层保持未蚀刻; 并且在栅极结构的栅极结构和多个层的上端表面上提供对准掩模间隔物，所述对准掩模间隔物有助于蚀刻多个层的另一层，以选择性地暴露部分端部表面 其他层。

公开(公告)号：US20160079168A1

公开(公告)日：2016-03-17

申请号：US14947259

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hiroaki NIIMI ,  Kisik CHOI ,  Hoon KIM ,  Andy WEI ,  Guillaume BOUCHE

IPC: H01L23/535

CPC classification number: H01L23/535 ,  H01L21/285 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.