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    Voltage-driven intelligent characterization bench for semiconductor
    12.
    发明授权
    Voltage-driven intelligent characterization bench for semiconductor 有权

    公开(公告)号：US09772371B2

    公开(公告)日：2017-09-26

    申请号：US14659793

    申请日：2015-03-17

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Charles J. Montrose ,  Ping-Chuan Wang

    IPC: G01R31/319 ,  G01R31/28 ,  G01R31/26 ,  G06F11/273 ,  G01R31/3193

    CPC classification number: G01R31/2834 ,  G01R31/2607 ,  G01R31/2851 ,  G01R31/31924 ,  G01R31/31935

    Abstract: A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

    Inducing device variation for security applications
    14.
    发明授权
    Inducing device variation for security applications 有权
    感应安全应用的设备变化

    公开(公告)号：US09576914B2

    公开(公告)日：2017-02-21

    申请号：US14707442

    申请日：2015-05-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

    IPC: H01L27/088 ,  H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/02

    CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

    Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

    Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

    INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
    15.
    发明申请
    INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS 有权
    诱导安全应用的设备变化

    公开(公告)号：US20160329287A1

    公开(公告)日：2016-11-10

    申请号：US14707442

    申请日：2015-05-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Wai-Kin Li ,  Chengwen Pei ,  Ping-Chuan Wang

    IPC: H01L23/00 ,  H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L23/576 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/66537 ,  H01L29/78

    Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.

    Abstract translation: 物理不可克隆功能（PUF）半导体器件包括半导体衬底，以及在半导体衬底中具有注入区域和覆盖区域的区域。 硬掩模覆盖了第一个覆盖区域，第二个覆盖区域。 具有第一离子浓度的第一植入区域和具有小于第一浓度的第二浓度的至少一个第二植入区域。 在这些区域上形成第一和第二FET。 第一和第二FET基于第一区域和至少一个第二区域相对于彼此具有电压阈值失配。

    Wafer thinning endpoint detection for TSV technology
    17.
    发明授权
    Wafer thinning endpoint detection for TSV technology 有权
    TSV技术的晶圆薄化端点检测

    公开(公告)号：US09349661B2

    公开(公告)日：2016-05-24

    申请号：US14161738

    申请日：2014-01-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hanyi Ding ,  Oleg Gluschenkov ,  Ping-Chuan Wang ,  Lin Zhou

    IPC: H01L21/78 ,  H01L21/66 ,  H01L21/768

    CPC classification number: H01L22/26 ,  H01L21/30625 ,  H01L21/76898 ,  H01L22/14

    Abstract: Embodiments of the present invention provide an apparatus and method for wafer thinning endpoint detection. Embodiments of the present invention utilize through silicon via (TSV) structures formed in the wafer. A specially made wafer handle is bonded to the wafer. Conductive slurry is used in the wafer backside thinning process. The wafer handle provides electrical connectivity to an electrical measurement tool, and conductive posts in the wafer handle are proximal to a test structure on the wafer. A plurality of electrically isolated TSVs is monitored via the electrical measurement tool. When the TSVs are exposed on the backside as a result of thinning, the conductive slurry shorts the electrically isolated TSVs, changing the electrical properties of the plurality of TSVs. The change in electrical properties is detected and used to trigger termination of the wafer backside thinning process.

    Abstract translation: 本发明的实施例提供了一种用于晶片薄化端点检测的装置和方法。 本发明的实施例利用在晶片中形成的硅通孔（TSV）结构。 特殊制造的晶圆把手与晶片结合。 导电浆料用于晶片背面变薄处理。 晶片手柄提供与电测量工具的电连接，并且晶片把手中的导电柱靠近晶片上的测试结构。 通过电测量工具监测多个电隔离TSV。 当TSV由于变薄而暴露在背面时，导电浆料使电隔离的TSV短路，改变多个TSV的电性能。 检测电特性的变化并用于触发晶圆背面变薄过程的终止。

    Integrated circuit structure with through-semiconductor via
    18.
    发明授权
    Integrated circuit structure with through-semiconductor via 有权
    具有贯通半导体通孔的集成电路结构

    公开(公告)号：US09318414B2

    公开(公告)日：2016-04-19

    申请号：US14065454

    申请日：2013-10-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Fen Chen ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

    IPC: H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

    Abstract translation: 本公开通常提供具有贯穿半导体通孔（TSV）的集成电路（IC）结构。 在一个实施例中，IC结构可以包括嵌入在衬底中的贯穿半导体通孔（TSV），TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔，每个通孔嵌入在电介质层内，并将金属层耦合到各个接触点处的TSV的盖，其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。

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