公开(公告)号：US20050142933A1

公开(公告)日：2005-06-30

申请号：US11013851

申请日：2004-12-16

Applicant: Gottfried Beer ,  Jochen Dangelmaier ,  Alfred Haimerl ,  Manfred Mengel ,  Klaus Mueller ,  Klaus Pressel

Inventor： Gottfried Beer ,  Jochen Dangelmaier ,  Alfred Haimerl ,  Manfred Mengel ,  Klaus Mueller ,  Klaus Pressel

IPC: B82B1/00 ,  H01L23/498 ,  H01L23/50 ,  H01R13/60

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/49877 ,  H01L24/05 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/14 ,  Y10S977/742 ,  Y10S977/932

Abstract: The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 μm, which rewiring plate includes a base body and passages with carbon nanotubes, the lower end of the passages opening out into contact connection surfaces, and the carbon nanotubes forming an electrically conductive connection from the contact connection surfaces to the front surface of the base body.

Abstract translation: 本发明描述了一种用于具有连接栅格的部件的再布线板， 100nm和10um，该再布线板包括基体和具有碳纳米管的通道，通道的下端开口成接触连接表面，并且碳纳米管从接触连接表面到前表面形成导电连接 的基体。

公开(公告)号：US06313729B1

公开(公告)日：2001-11-06

申请号：US09180128

申请日：1998-11-02

Applicant: Jürgen Winterer ,  Gottfried Beer

Inventor： Jürgen Winterer ,  Gottfried Beer

IPC: H01L1010

CPC classification number: G01L19/147 ,  G01L19/003 ,  G01L19/0038 ,  G01L19/0084 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor component is fashioned of a chip carrier comprising an approximately planar chip carrier surface on which chip carrier surface a semiconductor chip with a pressure sensor is secured, and composed of electrode terminals penetrating the chip carrier and electrically connected to the semiconductor chip, with a surface-mounted arrangement. The chip overlapping the chip carrier.

Abstract translation: 一种半导体部件由芯片载体构成，芯片载体包括大致平坦的芯片载体表面，芯片载体表面具有固定有压力传感器的半导体芯片，并且由穿过芯片载体并与半导体芯片电连接的电极端子组成， 表面安装。 该芯片与芯片载体重叠。

公开(公告)号：US09129959B2

公开(公告)日：2015-09-08

申请号：US13591055

申请日：2012-08-21

Applicant: Edward Fuergut ,  Irmgard Escher-Poeppel ,  Gottfried Beer

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Gottfried Beer

IPC: H01L21/50 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/498 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/82104 ,  H01L2224/96 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2224/82 ,  H01L2924/00

Abstract: A number of semiconductor chips each include a first main face and a second main face opposite from the first main face. The second main face includes at least one electrical contact element. The semiconductor chips are placed on a carrier. A material layer is applied into intermediate spaces between adjacent semiconductor chips. The carrier is removed and a first electrical contact layer is applied to the first main faces of the semiconductor chips so that the electrical contact layer is electrically connected with each one of the electrical contact elements.

Abstract translation: 多个半导体芯片各自包括与第一主面相对的第一主面和第二主面。 第二主面包括至少一个电接触元件。 将半导体芯片放置在载体上。 将材料层施加到相邻半导体芯片之间的中间空间。 移除载体并且将第一电接触层施加到半导体芯片的第一主面，使得电接触层与每个电接触元件电连接。

公开(公告)号：US08912638B2

公开(公告)日：2014-12-16

申请号：US13102452

申请日：2011-05-06

Applicant: Horst Theuss ,  Gottfried Beer

Inventor： Horst Theuss ,  Gottfried Beer

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  B81B7/00

CPC classification number: H01L21/568 ,  B81B7/007 ,  B81C2203/0109 ,  B81C2203/0154 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Abstract translation: 公开了一种包括芯片的装置，该芯片保持在铸造化合物中并且布置有中空结构。

公开(公告)号：US08338936B2

公开(公告)日：2012-12-25

申请号：US12179217

申请日：2008-07-24

Applicant: Klaus Pressel ,  Gottfried Beer

Inventor： Klaus Pressel ,  Gottfried Beer

IPC: H01L23/52

CPC classification number: G01P1/023 ,  B81B7/02 ,  B81B2207/092 ,  B81B2207/095 ,  B81C1/0023 ,  B81C2203/0154 ,  G01L9/0042 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/76155 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H04R1/04 ,  H04R2201/003 ,  H01L2224/82 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.

Abstract translation: 半导体器件及其制造方法。 一个实施例提供一种半导体芯片。 封装材料覆盖半导体芯片。 金属层在半导体芯片和封装材料之上。 电压产生单元和显示单元中的至少一个刚性地附接到至少一个封装材料和金属层。

公开(公告)号：US08330274B2

公开(公告)日：2012-12-11

申请号：US12893009

申请日：2010-09-29

Applicant: Hans-Joachim Barth ,  Gottfried Beer ,  Joern Plagmann ,  Jens Pohl ,  Werner Robl ,  Rainer Steiner ,  Mathias Vaupel

Inventor： Hans-Joachim Barth ,  Gottfried Beer ,  Joern Plagmann ,  Jens Pohl ,  Werner Robl ,  Rainer Steiner ,  Mathias Vaupel

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

公开(公告)号：US08318540B2

公开(公告)日：2012-11-27

申请号：US12122926

申请日：2008-05-19

Applicant: Gottfried Beer

Inventor： Gottfried Beer

IPC: H01L21/00

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/96 ,  H01L24/97 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.

Abstract translation: 一种制造半导体结构的方法。 一个实施例产生具有嵌入模制体中的至少两个半导体芯片的基板。 通过使用喷墨印刷方法将层施加在基板的至少一个主表面上。

公开(公告)号：US08169059B2

公开(公告)日：2012-05-01

申请号：US12242521

申请日：2008-09-30

Applicant: Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Oliver Nagy

Inventor： Hans-Joachim Barth ,  Jens Pohl ,  Gottfried Beer ,  Oliver Nagy

IPC: H01L23/552

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.

Abstract translation: 公开了一种片上系统的结构以及片上系统的形成方法。 在一个实施例中，芯片上的系统包括设置在基板的第一部分上的RF部件，设置在基板的第二部分上的半导体部件，共享公共边界的半导体部件和RF部件。 芯片上的系统还包括通过设置在基板中的基板导体，连接到地电位节点的贯穿基板导体，围绕RF元件设置的贯穿基板导体，围绕RF电路形成围栏。

公开(公告)号：US08148257B1

公开(公告)日：2012-04-03

申请号：US12894190

申请日：2010-09-30

Applicant: Hans-Joachim Barth ,  Gottfried Beer ,  Joern Plagmann ,  Jens Pohl ,  Werner Robl ,  Rainer Steiner ,  Mathias Vaupel

Inventor： Hans-Joachim Barth ,  Gottfried Beer ,  Joern Plagmann ,  Jens Pohl ,  Werner Robl ,  Rainer Steiner ,  Mathias Vaupel

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/469

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

Abstract translation: 一个或多个实施例涉及一种形成电子设备的方法，包括：提供工件; 在工件上形成第一阻挡层; 在所述第一阻挡层上形成中间导电层; 在所述中间导电层上形成第二阻挡层; 在所述第二阻挡层上形成种子层; 去除种子层的一部分以留下种子层的剩余部分并暴露第二阻挡层的一部分; 并在种子层的剩余部分上电镀填充层。

公开(公告)号：US20110101532A1

公开(公告)日：2011-05-05

申请号：US12611609

申请日：2009-11-03

Applicant: Jens Pohl ,  Hans-Joachim Barth ,  Gottfried Beer ,  Rainer Steiner ,  Werner Robl ,  Mathias Vaupel

Inventor： Jens Pohl ,  Hans-Joachim Barth ,  Gottfried Beer ,  Rainer Steiner ,  Werner Robl ,  Mathias Vaupel

IPC: H01L23/48 ,  H05K1/00 ,  C25D5/00 ,  C25D5/34

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/1089 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.

Abstract translation: 一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。 该方法包括在电介质层上施加第一种子层，在种子层上施加惰性层，以及构造惰性层，第一籽晶层和电介质层以暴露至少一部分接触。 该方法包括在结构化介电层和触点的暴露部分上施加第二种子层，使得第二籽晶层与结构化的第一籽晶层电接触。 该方法包括在第二种子层上电镀金属。