公开(公告)号：US20140319522A1

公开(公告)日：2014-10-30

申请号：US13870026

申请日：2013-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Abstract translation: 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 除去掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且将焊料材料沉积在凸块下焊盘上。

公开(公告)号：US20130140695A1

公开(公告)日：2013-06-06

申请号：US13758386

申请日：2013-02-04

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  George J. Scott

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/051 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01027 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。 该方法包括形成包含第一和第二导电层的层叠层，在第二导电层的顶表面上形成电介质钝化层，以及形成延伸穿过介电钝化层的通孔至第二导电层的顶表面。 该方法还包括在通孔开口中形成导电塞。 焊料凸点连接包括由不同导体组成的第一和第二导电层，在第二导电层的顶表面上的介电钝化层，延伸穿过介电钝化层到第二导电层顶表面的通孔，以及 导电塞在通孔开口中。

公开(公告)号：US20190244923A1

公开(公告)日：2019-08-08

申请号：US16390193

申请日：2019-04-22

Applicant: International Business Machines Corporation

Inventor： Krishna Tunga ,  Ekta Misra

IPC: H01L23/00

Abstract: The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

公开(公告)号：US20180108626A1

公开(公告)日：2018-04-19

申请号：US15642742

申请日：2017-07-06

Applicant: International Business Machines Corporation

Inventor： Ekta Misra ,  Krishna R. Tunga

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20150325540A1

公开(公告)日：2015-11-12

申请号：US14788945

申请日：2015-07-01

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

公开(公告)号：US09159696B2

公开(公告)日：2015-10-13

申请号：US14026158

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。 在电介质层上形成钝化层。 通孔开口从钝化层的顶表面延伸穿过钝化层到介电层中的金属线。 钝化层的顶表面上的掩模包括与通孔开口对准的掩模开口。 导电层选择性地形成在通路孔和掩模开口中。 导电层突出在钝化层的顶表面之上。 该方法还包括平坦化钝化层和导电层以限定与金属线耦合的通孔孔中的插塞。

公开(公告)号：US20150076688A1

公开(公告)日：2015-03-19

申请号：US14026158

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Ekta Misra ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/036 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。 在电介质层上形成钝化层。 通孔开口从钝化层的顶表面延伸穿过钝化层到介电层中的金属线。 钝化层的顶表面上的掩模包括与通孔开口对准的掩模开口。 导电层选择性地形成在通路孔和掩模开口中。 导电层突出在钝化层的顶表面之上。 该方法还包括平坦化钝化层和导电层以限定与金属线耦合的通孔孔中的插塞。

公开(公告)号：US08937009B2

公开(公告)日：2015-01-20

申请号：US13870026

申请日：2013-04-25

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC: H01L21/768 ,  H01L21/44 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Abstract translation: 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 去除掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且焊料材料沉积在凸块下焊盘上。

公开(公告)号：US10090271B1

公开(公告)日：2018-10-02

申请号：US15636038

申请日：2017-06-28

Applicant: International Business Machines Corporation

Inventor： Krishna Tunga ,  Ekta Misra

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528

Abstract: The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

公开(公告)号：US09214385B2

公开(公告)日：2015-12-15

申请号：US14202067

申请日：2014-03-10

Applicant: International Business Machines Corporation

Inventor： Brian M. Erwin ,  Karen P. McLaughlin ,  Ekta Misra

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/3171 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76816 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/1031 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

Abstract translation: 制造半导体器件的方法包括在半导体器件的至少一个覆盖层上形成钝化层，并在钝化层上形成密封剂层。 该方法还包括图案化封装层以暴露钝化层的一部分并在钝化层中形成最终的通孔。 导电材料沉积在最终通孔中。 该方法还包括平坦化导电材料，直到到达封装层的剩余部分，使得导电材料与密封剂层齐平并且保护钝化层。