公开(公告)号：US20160155695A1

公开(公告)日：2016-06-02

申请号：US15005220

申请日：2016-01-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 623) connect the dies to the cavity's bottom all (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

公开(公告)号：US11114408B2

公开(公告)日：2021-09-07

申请号：US16687498

申请日：2019-11-18

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/304 ,  H01L21/3105

Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

公开(公告)号：US11056390B2

公开(公告)日：2021-07-06

申请号：US16718820

申请日：2019-12-18

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US20190198435A1

公开(公告)日：2019-06-27

申请号：US16288720

申请日：2019-02-28

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065 ,  H01L23/10 ,  H01L21/56 ,  H01L25/16 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US10256177B2

公开(公告)日：2019-04-09

申请号：US15651826

申请日：2017-07-17

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC: H01L23/10 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US10178363B2

公开(公告)日：2019-01-08

申请号：US15280661

申请日：2016-09-29

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H04N9/04 ,  H04N9/43 ,  G02B27/10 ,  G06T1/20 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/33 ,  H04N5/374 ,  H04N9/097 ,  H04N9/76

Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US20180337118A1

公开(公告)日：2018-11-22

申请号：US16017010

申请日：2018-06-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US09947618B2

公开(公告)日：2018-04-17

申请号：US15619160

申请日：2017-06-09

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L21/44 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20180096973A1

公开(公告)日：2018-04-05

申请号：US15834658

申请日：2017-12-07

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/304 ,  H01L21/306 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L24/94 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/1436

Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

公开(公告)号：US09888584B2

公开(公告)日：2018-02-06

申请号：US14942781

申请日：2015-11-16

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh

IPC: H05K1/11 ,  H01L23/00 ,  H05K3/40 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L24/81 ,  H01L2224/81193 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/3431

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.