公开(公告)号：US20230170233A1

公开(公告)日：2023-06-01

申请号：US18160124

申请日：2023-01-26

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/68 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L21/67259 ,  G01B11/272 ,  H01L21/681 ,  H01L21/78 ,  H01L22/20 ,  H01L21/67092

Abstract: In an embodiment a method includes placing a wafer on a receptacle comprising a chuck base, wherein a light port for emitting light from a source of light is an opening located in a surface of the chuck base, and wherein the light port is located underneath the wafer, shining the light from the light port at an edge of the wafer so that light passes by the edge of the wafer and processing the wafer on the receptacle based on the light that passed by the edge of the wafer and that is received by a light sensitive element.

公开(公告)号：US20190122909A1

公开(公告)日：2019-04-25

申请号：US16220888

申请日：2018-12-14

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/66 ,  G01B11/27 ,  H01L21/68

Abstract: A method and apparatus for use in a wafer processing are disclosed. In an embodiment a includes providing the wafer on a receptacle, wherein the receptacle comprises a light port, and wherein the light port includes a source of light, shining a light from the source of light at an edge of the wafer thereby passing light by the edge of the wafer and processing the wafer on the receptacle based on the light passing by the edge of the wafer and received by a light sensitive element.

公开(公告)号：US10262959B2

公开(公告)日：2019-04-16

申请号：US15295631

申请日：2016-10-17

Applicant: Infineon Technologies AG

Inventor： Evelyn Napetschnig ,  Ulrike Fastner ,  Alexander Heinrich ,  Thomas Fischer

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/308 ,  H01L21/683 ,  H01L21/268 ,  H01L21/304 ,  H01L23/31

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

公开(公告)号：US10186438B2

公开(公告)日：2019-01-22

申请号：US14933931

申请日：2015-11-05

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/68 ,  H01L21/78 ,  H01L21/66

Abstract: A method and an apparatus for use in processing a wafer are disclosed. In an embodiment the method includes providing a wafer on a receptacle, shining a light at an edge of the wafer and based on light that passed the edge of the wafer, processing the wafer on the receptacle.

公开(公告)号：US20170076961A1

公开(公告)日：2017-03-16

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/56 ,  H01L27/02 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

Abstract translation: 提供了一种安排。 该布置可以包括：具有前侧和后侧的基板，基板内的管芯区域，限定管芯区域的背面的多用途层以及设置在多用途层之间的蚀刻停止层， 多用途层和背面。 多用途层可以由欧姆材料形成，并且蚀刻停止层可以是第一掺杂浓度的第一导电类型。

公开(公告)号：US09293409B2

公开(公告)日：2016-03-22

申请号：US14023493

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L21/784 ,  H01L23/482

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract translation: 根据各种实施例，半导体器件的制造方法可以包括提供半导体工件，其包括在半导体工件的第一侧的器件区域，其中半导体工件的机械稳定性不足以抵抗至少一个后端工艺，而没有 损坏，并且在半导体工件的与半导体工件的第一侧相对的第二侧上沉积至少一个导电层，其中至少一个导电层增加半导体工件的机械稳定性，以足以抵抗至少一个 后端程序无损坏。

公开(公告)号：US20150091183A1

公开(公告)日：2015-04-02

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。

公开(公告)号：US20140048940A1

公开(公告)日：2014-02-20

申请号：US14060734

申请日：2013-10-23

Applicant: Infineon Technologies AG

Inventor： Roland Hampp ,  Thomas Fischer ,  Uwe Hoeckele

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76837 ,  H01L21/76838 ,  H01L22/32 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03903 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06505 ,  H01L2224/06515 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0428 ,  H01L2924/0518 ,  H01L2924/0529 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device and method are disclosed. The semiconductor device includes a substrate having a first region and a second region and an insulating layer arranged on the substrate. A first conductive layer is arranged in or on insulating layer in the first region and a second conductive layer is arranged in or on the insulating layer in the second region. The first conductive layer comprises a first conductive material and the second conductive layer comprises a second conductive material wherein the first conductive material is different than the second conductive material. A metal layer is arranged on the first conductive layer.

Abstract translation: 公开了半导体器件和方法。 半导体器件包括具有第一区域和第二区域的衬底以及布置在衬底上的绝缘层。 第一导电层布置在第一区域中的绝缘层中或绝缘层中，并且第二导电层布置在第二区域中的绝缘层中或其上。 第一导电层包括第一导电材料，第二导电层包括第二导电材料，其中第一导电材料不同于第二导电材料。 金属层布置在第一导电层上。

公开(公告)号：US12148640B2

公开(公告)日：2024-11-19

申请号：US18160124

申请日：2023-01-26

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Gerald Lackner ,  Walter Horst Leitgeb ,  Michael Lecher

IPC: H01L21/67 ,  G01B11/27 ,  H01L21/66 ,  H01L21/68 ,  H01L21/78

Abstract: In an embodiment a method includes placing a wafer on a receptacle comprising a chuck base, wherein a light port for emitting light from a source of light is an opening located in a surface of the chuck base, and wherein the light port is located underneath the wafer, shining the light from the light port at an edge of the wafer so that light passes by the edge of the wafer and processing the wafer on the receptacle based on the light that passed by the edge of the wafer and that is received by a light sensitive element.

公开(公告)号：US11605572B2

公开(公告)日：2023-03-14

申请号：US17237143

申请日：2021-04-22

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Thomas Fischer ,  Uwe Seidel ,  Anton Steltenpohl

IPC: H01L23/31 ,  H01L21/683 ,  H01L23/29 ,  H01L23/00

Abstract: An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.