公开(公告)号：US20250118647A1

公开(公告)日：2025-04-10

申请号：US18988225

申请日：2024-12-19

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

公开(公告)号：US20250046680A1

公开(公告)日：2025-02-06

申请号：US18921373

申请日：2024-10-21

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20240071935A1

公开(公告)日：2024-02-29

申请号：US17895965

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80894 ,  H01L2224/80895

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

公开(公告)号：US20230101340A1

公开(公告)日：2023-03-30

申请号：US17485295

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kaveh HOSSEINI ,  Omkar KARHADE ,  Ravindranath V. MAHAJAN ,  Sergey Yuryevich SHUMARAYEV ,  Yew F. KOK ,  Sai VADLAMANI

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling an electronic package. In an embodiment, an electronic package comprises a package substrate with a stepped top surface, and a first die on a first plateau of the stepped top surface. In an embodiment, a second die is on a second plateau of the stepped top surface, where the second die extends over the first die, In an embodiment, a third die is on a third plateau of the stepped top surface, where the third die extends over the second die.

公开(公告)号：US20220413236A1

公开(公告)日：2022-12-29

申请号：US17358502

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Sushrutha Reddy GUJJULA ,  Tolga ACIKALIN ,  Ravindranath V. MAHAJAN ,  James E. JAUSSI ,  Chia-Pin CHIU

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01S3/04

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to thermally and/or electrically coupling a thermal die to the surface of a photonic integrated circuit (PIC) within an open cavity in a substrate, where the thermal die is proximate to a laser on the PIC. Other embodiments may be described and/or claimed.

公开(公告)号：US20170269017A1

公开(公告)日：2017-09-21

申请号：US15075083

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Steven A. KLEIN ,  Rajendra C. DIAS ,  David C. MCCOY ,  Lars D. SKOGLUND ,  Vijay SUBRAMANIAN ,  Aleksander ALEKSOV ,  Pramod MALATKAR ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: G01N27/20

CPC classification number: G01N27/20 ,  G01L1/04 ,  G01L1/18 ,  G01L1/22 ,  G01N3/08 ,  G01N2033/0078 ,  G01N2033/0095 ,  G01N2203/0042 ,  G01N2203/0044 ,  G01N2203/0062

Abstract: Embodiments are generally directed to air bladder based mechanical testing for stretchable electronics. An embodiment of a system includes an inflatable bladder to apply mechanical force to a stretchable electronics device by the inflation and deflation of the inflatable bladder; a valve unit to control fluid pressure applied to the inflatable bladder; and a control unit to control inflation and deflation of the inflatable bladder.

公开(公告)号：US20250029929A1

公开(公告)日：2025-01-23

申请号：US18907985

申请日：2024-10-07

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20230352412A1

公开(公告)日：2023-11-02

申请号：US18221184

申请日：2023-07-12

Applicant: Intel Corporation

Inventor： Yidnekachew S. MEKONNEN ,  Kemel AYGUN ,  Ravindranath V. MAHAJAN ,  Christopher S. BALDWIN ,  Rajasekaran SWAMINATHAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

公开(公告)号：US20220085001A1

公开(公告)日：2022-03-17

申请号：US17539088

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Suresh V. POTHUKUCHI ,  Andrew ALDUINO ,  Ravindranath V. MAHAJAN ,  Srikant NEKKANTY ,  Ling LIAO ,  Harinadh POTLURI ,  David M. BOND ,  Sushrutha Reddy GUJJULA ,  Donald Tiendung TRAN ,  David HUI ,  Vladimir TAMARKIN

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/473 ,  H01L23/538 ,  H04Q11/00

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.