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    Vertical inductor for WLCSP
    14.
    发明授权
    Vertical inductor for WLCSP 有权

    公开(公告)号：US11250981B2

    公开(公告)日：2022-02-15

    申请号：US16993152

    申请日：2020-08-13

    Applicant: Intel Corporation

    Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

    IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/00 ,  H01F27/28

    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

    Integrated circuit package having wirebonded multi-die stack
    19.
    发明授权
    Integrated circuit package having wirebonded multi-die stack 有权

    公开(公告)号：US10249598B2

    公开(公告)日：2019-04-02

    申请号：US15915769

    申请日：2018-03-08

    Applicant: INTEL CORPORATION

    Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

    IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

    Integrated circuit package
    20.
    发明授权
    Integrated circuit package 有权

    公开(公告)号：US10157869B2

    公开(公告)日：2018-12-18

    申请号：US15294499

    申请日：2016-10-14

    Applicant: Intel Corporation

    Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

    IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/525

    Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

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