公开(公告)号：US07674989B2

公开(公告)日：2010-03-09

申请号：US11449673

申请日：2006-06-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01R12/04

CPC分类号： H05K1/115 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

摘要翻译： 一种用于安装具有多个布线层的半导体元件或电子元件的布线板，设置在这些布线层之间的绝缘层，以及设置在绝缘层上并将布线层电连接的通孔。 在该布线板中，通过多个相似形状（圆圈）的部分重叠，获得与布线层平行的平面中的通孔的截面形状。 通过最小化增加密度的障碍物，有效地增加通孔的横截面积，并且通过使通孔的横截面形状成为由通孔形成的形状来防止布线电阻增加，可以在半导体元件中获得稳定的操作 多个类似形状的部分重叠。

公开(公告)号：US20090315190A1

公开(公告)日：2009-12-24

申请号：US12306987

申请日：2007-06-29

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Kentaro Mori ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H01L23/538 ,  H05K1/11 ,  H01L21/60 ,  H01L21/31

CPC分类号： H05K3/205 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/244 ,  H05K3/423 ,  H05K2201/0338 ,  H05K2201/098 ,  H05K2201/09845 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.

摘要翻译： 布线基板具有绝缘层，多个布线层以通过绝缘层彼此绝缘的方式形成，以及形成在绝缘层中以连接布线层的多个通孔。 在布线层中，形成在绝缘层的一个表面上的表面布线层包括从一个表面露出的第一金属膜和嵌入在绝缘层中并叠放在第一金属膜上的第二金属膜。 第一金属膜的边缘沿着第二金属膜扩展的方向从第二金属膜的边缘突出。 通过以这种方式设计嵌入在绝缘层中的布线层的形状，可以获得在制造过程中可以有效地防止侧蚀刻的高可靠性布线板，并且可以适应电线的小型化和高密度封装 。

公开(公告)号：US20080012140A1

公开(公告)日：2008-01-17

申请号：US11822599

申请日：2007-07-09

申请人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

发明人： Jun Tsukano ,  Kenta Ogawa ,  Takehiko Maeda ,  Shintaro Yamamichi ,  Katsumi Kikuchi

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H05K1/0271 ,  H01L21/4846 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/09018 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate.

摘要翻译： 布线基板包括基底绝缘膜，形成在基底绝缘膜的上表面侧上的第一互连，设置在形成在基底绝缘膜中的通孔中的通孔导体，以及设置在基底绝缘膜的底面侧的第二互连 基底绝缘膜，第二互连件经由通孔导体连接到第一互连件。 布线基板包括分割的基板单元区域，其中形成有第一互连，通孔导体和第二互连。 布线基板包括在基底绝缘膜上的翘曲控制图案，并且具有翘曲形状，使得当布线基板静止在水平板上时，基板的平面的每一侧的至少中心部分 接触水平板，其侧面的两端被凸起，其中每个侧面沿着垂直于基板的平面表面中的第一方向的第二方向延伸。

公开(公告)号：US20060283629A1

公开(公告)日：2006-12-21

申请号：US11449673

申请日：2006-06-09

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Hideya Murai ,  Takuo Funaya ,  Takehiko Maeda ,  Hirokazu Honda ,  Kenta Ogawa ,  Jun Tsukano

IPC分类号： H05K1/11 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2203/1476 ,  Y10T29/49165

摘要： A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.

摘要翻译： 一种用于安装具有多个布线层的半导体元件或电子元件的布线板，设置在这些布线层之间的绝缘层，以及设置在绝缘层上并将布线层电连接的通孔。 在该布线板中，通过多个相似形状（圆圈）的部分重叠，获得与布线层平行的平面中的通孔的横截面形状。 通过最小化增加密度的障碍物，有效地增加通孔的横截面积，并且通过使通孔的横截面形状成为由通孔形成的形状来防止布线电阻增加，可以在半导体元件中获得稳定的操作 多个类似形状的部分重叠。

公开(公告)号：US08357935B2

公开(公告)日：2013-01-22

申请号：US13137247

申请日：2011-08-01

申请人： Yasuhiro Matsumaru ,  Kenta Ogawa

发明人： Yasuhiro Matsumaru ,  Kenta Ogawa

IPC分类号： H01L23/58 ,  H01L29/10 ,  H01L23/544 ,  H01L21/66 ,  H01L21/76 ,  H01L21/00 ,  G01R31/26

CPC分类号： H01L21/56 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/16 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/0401

摘要： In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.

摘要翻译： 为了解决上述问题，提供了一种具有形成在暴露表面上的认证图案的电子部件，其中认证图案包括具有树脂的基部和具有可在基部中识别的色调的着色颗粒， 并且着色颗粒被分散以在基部中形成点状图案。

公开(公告)号：US08283770B2

公开(公告)日：2012-10-09

申请号：US13067548

申请日：2011-06-08

申请人： Yasutaka Nakashiba ,  Kenta Ogawa

发明人： Yasutaka Nakashiba ,  Kenta Ogawa

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/645 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor module includes a semiconductor device including a mounting board, a semiconductor chip disposed at a first surface of the mounting board, a first inductor which is provided at a surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside, a sealing resin layer which is formed at the first surface of the mounting board in order to seal the semiconductor chip, and a recess or an opening which is provided in the sealing resin layer and which includes the inductor inside when seen in a plan view; and a second inductor, which is located in the recess or the opening of the semiconductor device so that the second inductor performs communication with the first inductor.

摘要翻译： 半导体模块包括：半导体器件，包括安装板，设置在安装板的第一表面的半导体芯片;第一电感器，设置在不面向安装板的半导体芯片的表面侧，以便执行 半导体芯片和外部，形成在安装板的第一表面以密封半导体芯片的密封树脂层，以及设置在密封树脂层中并且包括电感器内部的凹部或开口的密封树脂层 当在平面图中看到; 以及第二电感器，其位于半导体器件的凹部或开口中，使得第二电感器执行与第一电感器的连通。

公开(公告)号：US20110143662A1

公开(公告)日：2011-06-16

申请号：US12926709

申请日：2010-12-06

申请人： Yasutaka Nakashiba ,  Kenta Ogawa

发明人： Yasutaka Nakashiba ,  Kenta Ogawa

IPC分类号： H04B5/00 ,  H01L29/66

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/645 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip is disposed on a first surface of a mounting board with its active surface upward. An inductor is provided at the active surface side, that is, at the surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside. A sealing resin layer is formed on the first surface of the mounting board in order to seal the semiconductor chip. In addition, a recess or an opening (in the present embodiment, a recess) is provided in the sealing resin layer. The recess includes the inductor thereinside when seen in a plan view.

摘要翻译： 半导体芯片设置在其主动表面向上的安装板的第一表面上。 在半导体芯片的表面侧，在半导体芯片与外部之间进行通信时，在有源面侧设置电感器，不面向安装基板。 为了密封半导体芯片，在安装基板的第一面上形成密封树脂层。 此外，在密封树脂层中设置有凹部或开口（在本实施方式中为凹部）。 当在平面图中看时，该凹槽包括其内部的电感器。

公开(公告)号：US20110141681A1

公开(公告)日：2011-06-16

申请号：US12926710

申请日：2010-12-06

申请人： Yasutaka Nakashiba ,  Kenta Ogawa

发明人： Yasutaka Nakashiba ,  Kenta Ogawa

IPC分类号： G06F1/16 ,  H05K3/30

CPC分类号： H01L28/10 ,  G11C5/005 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0949 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/1316 ,  H05K2203/1572 ,  Y10T29/4902 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.

摘要翻译： 存储元件设置在半导体芯片中，并且电感器和驱动电路设置在另一半导体芯片中。 外部端子是接触型端子，至少一些外部端子是电源端子和接地端子。 在互连基板的第一表面上形成密封树脂层，并密封半导体芯片，但不覆盖外部端子。 电感器形成在不面向互连基板的半导体芯片的表面。

公开(公告)号：US20050056446A1

公开(公告)日：2005-03-17

申请号：US10937380

申请日：2004-09-10

申请人： Kenta Ogawa

发明人： Kenta Ogawa

IPC分类号： C23C30/00 ,  B32B15/01 ,  C25D5/02 ,  H01L21/60 ,  H01L23/495 ,  H01L23/50 ,  H02G3/08

CPC分类号： H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/29339 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S428/935 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/43

摘要： An external terminal of an electronic component is provided with a lead base material and a metal thin film coating a surface of the lead base material, and an average value of a crystal size index is not less than 7, which is defined based on dimensions of a crystal particle in a direction perpendicular to the lead base material surface and in a direction parallel thereto, taken on a cut surface of the metal thin film defined by a given plane cutting the metal thin film in a direction perpendicular to the lead base material surface. Such constitution provides an electronic component having an external terminal coated with a metal thin film of a simple structure constituted of Sn or a Sn-based and substantially Pb-free alloy, formed by plating on a surface of a lead base material. Yet such electronic component can effectively restrain emergence of a whisker on the outer plated layer under a circumstance of practical use.

摘要翻译： 电子部件的外部端子设置有铅基材料和涂覆铅基材的表面的金属薄膜，并且晶体尺寸指数的平均值不小于7，其基于 在垂直于铅基材料表面的方向上并且沿与其平行的方向的方向上的晶体颗粒被取入在由垂直于引线基材表面的方向切割金属薄膜的给定平面限定的金属薄膜的切割表面上 。 这种结构提供了一种电子部件，其具有涂覆有由Sn或Sn基且基本上不含Pb的合金构成的简单结构的金属薄膜的外部端子，该合金通过在铅基材料的表面上电镀而形成。 然而，这样的电子部件可以在实际使用的情况下有效地抑制外镀层上的晶须的出现。

公开(公告)号：US06391179B1

公开(公告)日：2002-05-21

申请号：US09624335

申请日：2000-07-24

申请人： Kenta Ogawa

发明人： Kenta Ogawa

IPC分类号： C25D2100

CPC分类号： C25D21/12 ,  C25D17/10

摘要： The present invention provides a plating apparatus comprising: a plating bath filled with a plating solution; at least an anode in the plating solution; at least a plating object which serves as a cathode in the plating solution, so that the at least plating object is distanced from the at least anode; and at least a dummy cathode in the plating solution, so that the at least dummy cathode is applied with voltage to suppress a substitute-deposition of metal ions in the plating solution.

摘要翻译： 本发明提供一种电镀装置，其特征在于，包括：填充有镀液的电镀液; 电镀溶液中的至少阳极; 至少镀覆对象，其在所述电镀溶液中用作阴极，使得所述至少电镀对象远离所述至少阳极; 以及至少在电镀液中的虚拟阴极，使得至少具有虚拟阴极的电压被施加以抑制电镀溶液中的金属离子的替代沉积。