公开(公告)号：US20060157775A1

公开(公告)日：2006-07-20

申请号：US11378295

申请日：2006-03-20

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

公开(公告)号：US20060141708A1

公开(公告)日：2006-06-29

申请号：US11248691

申请日：2005-10-12

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L29/7923 ,  Y10S438/954

摘要： In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memory device includes forming the control gate within a trench formed in a semiconductor substrate, and forming charge storing regions in the semiconductor substrate on both sides of the control gate in a self-aligning manner, thereby allowing for multi-level cell operation.

摘要翻译： 在具有埋地控制栅极的非易失性存储器件中，增加控制栅极的有效沟道长度以限制穿通，并且增加用于存储电荷的区域以获得有利的大容量。 一种制造存储器件的方法包括：在形成于半导体衬底中的沟槽内形成控制栅极，并以自对准的方式在控制栅极两侧的半导体衬底中形成电荷存储区域，从而允许多级 电池操作。

公开(公告)号：US08963580B2

公开(公告)日：2015-02-24

申请号：US13597732

申请日：2012-08-29

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17756

摘要： A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

摘要翻译： 逻辑设备可以包括第一功能块，第一功能块包括第一存储块，第二存储块和第一功能控制器。 在第一操作时间段中，第一功能控制器可以被配置为接收第一配置选择信号和指示第一功能的第一配置命令信号，在第一操作时间中选择第一存储块作为配置的存储块 基于第一配置选择信号，并且基于第一配置命令信号来配置第一存储块中的第一功能。

公开(公告)号：US20120088360A1

公开(公告)日：2012-04-12

申请号：US13326700

申请日：2011-12-15

申请人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

发明人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/51 ,  H01L29/513

摘要： Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

摘要翻译： 制造包括多层电介质层的半导体器件的方法可以包括在半导体衬底上形成金属氧化物层，并在金属氧化物层上形成包含金属原子和硅原子的多层硅酸盐层。 硅酸盐层的多层可以包括具有不同硅浓度的至少两个金属硅酸盐层，其是包含在金属硅酸盐层中的所有金属原子和硅原子之间的硅原子的比率。

公开(公告)号：US07902609B2

公开(公告)日：2011-03-08

申请号：US12621079

申请日：2009-11-18

申请人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

发明人： Seo-woo Nam ,  Ki-chul Kim ,  Young-joon Moon ,  Jae-ouk Choo ,  Hong-jae Shin ,  Nae-in Lee

IPC分类号： H01L23/62

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L27/088 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.

摘要翻译： 半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和 第二晶体管区域并具有第三栅电极。 第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。 第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。 与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。 还描述了相关方法。

公开(公告)号：US07202524B2

公开(公告)日：2007-04-10

申请号：US11061747

申请日：2005-02-22

申请人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

发明人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42336

摘要： A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench. An inter-gate insulating layer is formed on the upper portion of floating gate and interposed between the floating gate and the control gate, and a drain region is formed in the surface of the substrate adjacent the control gate and spaced from the second sidewall of the trench.

摘要翻译： 提供一种非易失性存储器件，其包括浮置栅极，该浮置栅极具有形成在衬底表面中的沟槽中的下部，以及从下部突出到衬底表面上方的上部。 栅极绝缘层沿着沟槽的内壁形成并插入在沟槽和浮动栅极的下部之间。 源极区域形成在与沟槽的第一侧壁相邻的衬底中。 具有第一部分的控制栅极形成在邻近沟槽的第二侧壁的衬底的表面上方，并且第二部分形成在浮动栅极的上部并且从第一部分延伸。 沟槽的第一侧壁与沟槽的第二侧壁相对。 栅极间绝缘层形成在浮置栅极的上部并且插入在浮置栅极和控制栅极之间，并且漏极区域形成在基板的与控制栅极相邻的表面中并与第二侧壁间隔开 沟。

公开(公告)号：US07144771B2

公开(公告)日：2006-12-05

申请号：US10616056

申请日：2003-07-09

申请人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

发明人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

IPC分类号： H01L21/8242

CPC分类号： H01L21/02186 ,  C23C16/405 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

摘要翻译： 形成电子器件的方法包括提供第一电极，在第一电极上提供电介质氧化物层，并在电介质氧化物层上提供第二电极，使得电介质氧化物层位于第一和第二电极之间。 更具体地，与第一电极相邻的电介质氧化物层的第一部分可以具有第一密度的钛，并且与第一电极相对的电介质氧化物层的第二部分可具有不同于第一密度的钛的第二密度。 还讨论了相关结构。

公开(公告)号：US20060033152A1

公开(公告)日：2006-02-16

申请号：US11183614

申请日：2005-07-18

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

公开(公告)号：US06893501B2

公开(公告)日：2005-05-17

申请号：US10320407

申请日：2002-12-17

申请人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

发明人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  C30B25/04

CPC分类号： H01L28/57 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/1085 ,  H01L28/65

摘要： A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

摘要翻译： 一种覆盖半导体存储器件的电容器，优选金属 - 绝缘体 - 金属（MIM）电容器的覆盖层的方法，其中所述方法包括在半导体上形成具有下电极，电介质层和上电极的电容器 衬底，在电容器上形成覆盖层，并使介电层结晶。 这里，形成覆盖层包括在不提供氧气的情况下沉积封盖层的稳定性，通过为封盖层提供反应源沉积覆盖层; 并且清洗用于形成覆盖层的反应器的内部。

公开(公告)号：US08969188B2

公开(公告)日：2015-03-03

申请号：US13326700

申请日：2011-12-15

申请人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

发明人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/28 ,  H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/51 ,  H01L29/513

摘要： Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

摘要翻译： 制造包括多层电介质层的半导体器件的方法可以包括在半导体衬底上形成金属氧化物层，并在金属氧化物层上形成包含金属原子和硅原子的多层硅酸盐层。 硅酸盐层的多层可以包括具有不同硅浓度的至少两个金属硅酸盐层，其是包含在金属硅酸盐层中的所有金属原子和硅原子之间的硅原子的比率。