公开(公告)号：US20170207139A1

公开(公告)日：2017-07-20

申请号：US15478133

申请日：2017-04-03

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02163 ,  H01L2224/0391 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US20170148769A1

公开(公告)日：2017-05-25

申请号：US15425956

申请日：2017-02-06

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

公开(公告)号：US09564418B2

公开(公告)日：2017-02-07

申请号：US14509912

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract translation: 本文公开了与金属间钯接头的互连结构。 在一个实施例中，形成互连结构的方法包括将包含镍的第一导电材料沉积在第一裸片的第一导电表面上，以及将包含镍的第二导电材料沉积在与第二裸片间隔开的第二导体的第二导电表面上 第一表面。 该方法还包括在第二导电材料上沉积第三导电材料，以及在第一和第三导电材料之间热压压锡/焊料以形成在第一导电材料和第二导电材料之间延伸的金属间钯接头，使得一端 的金属间接头的接头直接接合到第一导电材料上，金属间接头的另一端直接接合到第二导电材料上。

公开(公告)号：US20160343689A1

公开(公告)日：2016-11-24

申请号：US15229618

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

公开(公告)号：US20160293519A1

公开(公告)日：2016-10-06

申请号：US14678085

申请日：2015-04-03

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02125 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

Abstract translation: 本文描述了具有穿硅通孔的半导体器件及其形成方法。 作为示例，半导体器件可以包括衬底材料，从衬底材料延伸的穿硅通孔突出部，形成在衬底材料上的第一电介质材料，形成在第一电介质材料上的第二电介质材料，以及互连 形成在穿通硅通孔突起上，其中形成的互连在第二介电材料的开口中。

公开(公告)号：US20160284626A1

公开(公告)日：2016-09-29

申请号：US14667924

申请日：2015-03-25

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: Semiconductor devices having a conductive via and methods of forming the same are described herein. As an example, a semiconductor devices may include a conductive via formed in a substrate material, a barrier material, a first dielectric material on the barrier material, a coupling material formed on the substrate material and on at least a portion of the dielectric material, a second dielectric material formed on the coupling material, and an interconnect formed on the conductive via.

Abstract translation: 本文描述了具有导电通孔的半导体器件及其形成方法。 作为示例，半导体器件可以包括形成在衬底材料中的导电通孔，阻挡材料，阻挡材料上的第一介电材料，形成在衬底材料上的耦合材料和介电材料的至少一部分上的耦合材料， 形成在耦合材料上的第二电介质材料和形成在导电通路上的互连。

公开(公告)号：US20160104693A1

公开(公告)日：2016-04-14

申请号：US14509912

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract translation: 本文公开了与金属间钯接头的互连结构。 在一个实施例中，形成互连结构的方法包括将包含镍的第一导电材料沉积在第一裸片的第一导电表面上，以及将包含镍的第二导电材料沉积在与第二裸片间隔开的第二导体的第二导电表面上 第一表面。 该方法还包括在第二导电材料上沉积第三导电材料，以及在第一和第三导电材料之间热压压锡/焊料以形成在第一导电材料和第二导电材料之间延伸的金属间钯接头，使得一端 的金属间接头的接头直接接合到第一导电材料上，金属间接头的另一端直接接合到第二导电材料上。

公开(公告)号：US20150340328A1

公开(公告)日：2015-11-26

申请号：US14282606

申请日：2014-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/05023 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/8181 ,  H01L2924/3656 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/0103 ,  H01L2924/01079 ,  H01L2924/01029

Abstract: A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.

Abstract translation: 一种形成半导体器件组件的方法包括在第一衬底上形成至少一个焊接垫，该焊盘包括第一衬底上的第一镍材料，第一镍材料上的第一铜材料和第一铜上的焊料润湿材料 材料。 在第二基板上形成至少一个包括第二镍材料的导电柱，与第二镍材料直接接触的第二铜材料和直接接触第二铜材料的焊料材料。 焊料润湿材料与焊料材料接触。 将第一铜材料，焊料润湿材料，第二铜材料和焊料材料转化为基本均匀的金属间化合物互连结构。 还描述了另外的方法，半导体器件组件和互连结构。

公开(公告)号：US20150221612A1

公开(公告)日：2015-08-06

申请号：US14171169

申请日：2014-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  Michel Koopmans

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/06102 ,  H01L2224/06519 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/00012

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Abstract translation: 描述了通过在堆叠中的模具之间包括金属热垫来改善堆叠半导体管芯的散热的系统和方法。 在一个实施例中，热焊盘可以与半导体管芯直接接触。 半导体管芯堆叠的散热可以通过直接接触堆叠中的相邻硅管芯而不需要低导热材料（例如，钝化材料）的中间层的热焊盘的相对较高的热导率来改善。 在一些实施例中，可以通过具有热焊盘和凸块下金属化（UBM）结构的大致共面的顶表面来改善堆叠的制造产量。

公开(公告)号：US20150214160A1

公开(公告)日：2015-07-30

申请号：US14679845

申请日：2015-04-06

Applicant: Micron Technology, Inc.

Inventor： Mark A. Bossler ,  Jaspreet S. Gandhi ,  Christopher J. Gambee ,  Randall S. Parker

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/02068 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.

Abstract translation: 一种用于从衬底选择性地去除材料的方法，而不损害填充通孔的铜，并且至少部分地延伸通过衬底。 该方法包括氧化包括基底和至少一个铜特征的半导体结构，并且使用包含SF 6的蚀刻剂去除一部分基底，而不在至少一个铜特征上形成硫化铜。 还公开了另外的方法，以及由这些方法制备的半导体结构。