公开(公告)号：US06825553B2

公开(公告)日：2004-11-30

申请号：US10656352

申请日：2003-09-05

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L2352

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

公开(公告)号：US07843050B2

公开(公告)日：2010-11-30

申请号：US11863425

申请日：2007-09-28

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

摘要： Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

摘要翻译： 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US07553697B2

公开(公告)日：2009-06-30

申请号：US11595067

申请日：2006-11-09

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

摘要翻译： 公开了一种半导体器件封装及其制造方法。 半导体器件封装可以包括各种半导体管芯，从而提供芯片上的系统解决方案。 半导体裸片连接到与导电迹线层相关联的连接位置，例如通过倒装芯片技术。 多个电路连接元件也直接地或通过附加的中间导电迹线层耦合到导电迹线层。 可以在骰子和衬底之上形成封装层。 电路连接元件的一部分通过封装层保持暴露，以连接到外部设备。 可以形成多个导电凸块，每个导电凸块设置在电路连接元件的暴露部分的顶部，以便于与外部装置的电连接。

公开(公告)号：US20090014858A1

公开(公告)日：2009-01-15

申请号：US11846928

申请日：2007-08-29

申请人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

发明人： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

摘要翻译： 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US07304375B2

公开(公告)日：2007-12-04

申请号：US11222462

申请日：2005-09-07

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

摘要翻译： 提供了用于封装晶圆级封装中集成电路芯片的系统和方法。 芯片的有源电路区域耦合到城堡块，并且根据实施例，输入/输出焊盘。 城堡块和输入/输出垫通过密封剂封装并保持就位。 当制造设备时，将城堡块和输入/输出垫片穿过。 如果需要，可以使其上制造器件的晶片部分变薄。 封装可以用作无引线芯片载体封装，或者可以堆叠在彼此之上。 当堆叠时，封装的相应触点优选地联接。 当芯片被激活时，可以将数据写入和从芯片接收。 可以通过将适当的信号或信号施加到适当的触点或触点来激活芯片。

公开(公告)号：US07173330B2

公开(公告)日：2007-02-06

申请号：US11171124

申请日：2005-06-30

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L23/12 ,  H01L23/053

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

公开(公告)号：US06987031B2

公开(公告)日：2006-01-17

申请号：US10229908

申请日：2002-08-27

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

摘要翻译： 一种半导体器件封装及其制造方法。 半导体器件封装可以包括各种半导体管芯，从而提供芯片上的系统解决方案。 半导体裸片连接到与导电迹线层相关联的连接位置，例如通过倒装芯片技术。 多个电路连接元件也直接地或通过附加的中间导电迹线层耦合到导电迹线层。 可以在骰子和衬底之上形成封装层。 电路连接元件的一部分通过封装层保持暴露，以连接到外部设备。 可以形成多个导电凸块，每个导电凸块设置在电路连接元件的暴露部分的顶部，以便于与外部装置的电连接。

公开(公告)号：US20050116337A1

公开(公告)日：2005-06-02

申请号：US11028374

申请日：2005-01-03

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Shuangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Shuangwu Huang ,  Wei Zhou

IPC分类号： H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H01L23/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/34

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底的背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。 还公开了包含包装的计算系统。

公开(公告)号：US08445330B2

公开(公告)日：2013-05-21

申请号：US13459801

申请日：2012-04-30

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng

IPC分类号： H01L21/00 ,  H01L23/48

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49861 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15331

摘要： Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

摘要翻译： 封装的半导体器件和组件，包括用于形成这种互连的互连和方法。 封装半导体组件的一个实施例包括附接到支撑层的裸片。 多个互连嵌入在支撑层中并从支撑层突出，使得支撑层至少部分地将互连保持在预定的阵列中。 围绕每个互连件模制密封剂并且包封芯片，支撑层和互连件的至少一部分。

公开(公告)号：US08063493B2

公开(公告)日：2011-11-22

申请号：US12627352

申请日：2009-11-30

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

摘要翻译： 用于制造具有边缘触点的半导体器件组件和封装的牺牲衬底包括其表面上的导电元件，其被定位成沿着设备衬底上的每个相邻的一对半导体器件之间的街道排列。 半导体器件组件或封装包括半导体器件，半导体器件的有源表面上的再分布层，以及涂覆半导体器件外周的至少部分的电介质材料。 触点的周边部分位于外围边缘，并通过电介质涂层与其隔离。 触点还可以包括在半导体器件的有效表面上部分延伸的上部部分。 组件或封装可以包括任何类型的半导体器件，包括处理器，存储器件和发射极，或光敏器件。