公开(公告)号：US20090032964A1

公开(公告)日：2009-02-05

申请号：US11888122

申请日：2007-07-31

申请人： Warren Farnworth ,  Kyle Kirby

发明人： Warren Farnworth ,  Kyle Kirby

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/525 ,  H01L24/10 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2224/05552 ,  H01L2924/00

摘要： Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material.

摘要翻译： 本实施例涉及在涂覆操作期间使用保护层提供半导体器件特征的系统和方法。 一个实施例包括一种方法，其包括提供基底部分穿过其中形成的孔，所述孔包括在所述基底的第一侧中的开口。 另外，该方法包括在衬底的第一侧上设置保护层，在开口的至少一部分上移除保护层的一部分以提供对孔的接近，以及用孔填充孔的至少一部分 填充材料。

公开(公告)号：US20080029851A1

公开(公告)日：2008-02-07

申请号：US11868899

申请日：2007-10-08

申请人： Kyle Kirby ,  Warren Farnworth

发明人： Kyle Kirby ,  Warren Farnworth

IPC分类号： H01L29/40

CPC分类号： B82Y10/00 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/1094 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller through-holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.

摘要翻译： 形成多导体通孔的方法包括在衬底的至少一个通孔中形成至少一个种子层，选择性地图案化种子层以形成多个横向分离的区域，并在该区域上沉积金属。 或者，通孔可以基本上填充有介电材料，可以在电介质材料中形成多个较小的通孔，并且导电材料可以沉积在较小的孔中。 另一种方法包括在衬底的空腔中形成横向分离的突出结构，在结构之间沉积导电材料并在该结构之间沉积电介质材料，并使衬底变薄。 或者，可以在空腔中形成导电纳米管，并且可以沉积围绕纳米管的电介质材料。 一种形成多芯片模块的方法包括形成至少一个通过包括多个导电元件的多个堆叠的骰子延伸的通孔。

公开(公告)号：US20080011815A1

公开(公告)日：2008-01-17

申请号：US11777137

申请日：2007-07-12

申请人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

发明人： Kyle Kirby ,  Salman Akram ,  Daniel Cram ,  Roy Lange ,  Warren Farnworth

IPC分类号： B23K31/02

CPC分类号： B23K1/085 ,  B23K1/0016 ,  B23K3/0653 ,  B23K2101/40

摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.

摘要翻译： 描述了将半导体晶片或其它基板与焊料接触的方法和装置。 波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。 在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。 另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。 还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

公开(公告)号：US20070285115A1

公开(公告)日：2007-12-13

申请号：US11841566

申请日：2007-08-20

申请人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

发明人： Alan Wood ,  Tim Corbett ,  Warren Farnworth

IPC分类号： G01R31/02 ,  G01R1/06

CPC分类号： G01R31/2863

摘要： A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

摘要翻译： 用于测试半导体晶片上的无引脚骰子的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

公开(公告)号：US20070170350A1

公开(公告)日：2007-07-26

申请号：US11727545

申请日：2007-03-27

申请人： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

发明人： Warren Farnworth ,  Sidney Rigg ,  William Hiatt ,  Alan Wood ,  Peter Benson ,  James Wark ,  David Hembree ,  Kyle Kirby ,  Charles Watkins ,  Salman Akram

IPC分类号： H01L27/00

CPC分类号： H01L27/00 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/00014

摘要： Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

公开(公告)号：US20070134359A1

公开(公告)日：2007-06-14

申请号：US11702473

申请日：2007-02-05

申请人： Warren Farnworth

发明人： Warren Farnworth

IPC分类号： B29C35/08

CPC分类号： G03F7/70416 ,  B29C64/106 ,  B29C64/135 ,  B33Y30/00 ,  B33Y40/00 ,  B33Y50/02 ,  G03F7/0037

摘要： An apparatus for providing gross location, planarization, and mechanical restraint to one or more electronic components such as semiconductor dice to be subjected to stereolithographic processing. A double platen assembly including a first platen and a second platen mutually removably connected and configured and arranged to substantially secure an electronic component assembly in position therebetween. At least one of the platens is configured such that a portion of electronic components of a carrier substrate secured by the double platen assembly is viewable for exposure to an energy beam such as a laser beam used to cure a liquid into an associated dielectric stereolithographic packaging structure. Another embodiment includes the use of an adhesive-coated film for holding, locating and securing a plurality of individual electronic components for processing. A method of forming solder balls is also disclosed.

摘要翻译： 一种用于向诸如要进行立体光刻处理的半导体晶片的一个或多个电子部件提供总位置，平面化和机械约束的装置。 双压板组件包括第一压板和第二压板，所述第一压板和第二压板相互可拆卸地连接并构造和布置成基本上将电子部件组件固定在其间的适当位置。 至少一个压板被构造成使得由双压板组件固定的载体基板的电子部件的一部分可见以暴露于能量束，例如用于将液体固化成相关的介电立体光刻封装结构的激光束 。 另一个实施例包括使用粘合剂涂覆膜来保持，定位和固定多个单独的电子部件进行加工。 还公开了形成焊球的方法。

公开(公告)号：US20070075725A1

公开(公告)日：2007-04-05

申请号：US11607367

申请日：2006-12-01

申请人： Warren Farnworth ,  William Waller ,  Leland Nevill ,  Raymond Beffa ,  Eugene Cloud

发明人： Warren Farnworth ,  William Waller ,  Leland Nevill ,  Raymond Beffa ,  Eugene Cloud

IPC分类号： G01R31/26

CPC分类号： G01R31/025 ,  G01R31/2884

摘要： A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated.

摘要翻译： 用于将形成在半导体晶片的表面上的短路集成电路（IC）与形成在晶片上的与短路IC互连的其他IC隔离的电路包括用于感测短路IC的短路IC内的控制电路 电路。 控制电路可以以各种方式感测短路，包括感测由短路IC吸引的过电流，以及感测短路IC内的异常低或高电压。 短路IC内的开关电路响应于控制电路感测短路而选择性地将短路IC与晶片上的其它IC隔离。 结果，如果晶片处于探针测试之下，例如，在短路IC隔离的同时，其它IC上的测试可以不中断地继续。

公开(公告)号：US20070067064A1

公开(公告)日：2007-03-22

申请号：US11601968

申请日：2006-11-20

申请人： Warren Farnworth

发明人： Warren Farnworth

IPC分类号： G05D9/00

CPC分类号： H01L21/4763 ,  B29C64/106 ,  B29C64/135 ,  G03F7/0037 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/445 ,  H05K2203/107 ,  H05K2203/1476 ,  H01L2924/00

摘要： A surface level control system for use with a fabrication tank of a programmable material consolidation apparatus includes at least one aperture with a lowermost edge located at about the same elevation as a desired surface level for unconsolidated material within the fabrication tank. The surface level control system may also include a receptacle for receiving unconsolidated material that has been removed from the fabrication tank. The surface level control system may be configured to constantly allow for the removal of unconsolidated material, or it may be configured to selectively remove unconsolidated material. One or more sensors may be used to monitor the surface level and provide information that may be used in maintaining the surface level at a substantially constant elevation. A recycling system may be used in conjunction with or separately from a surface level control system to reintroduce unconsolidated material back into the fabrication tank.

摘要翻译： 与可编程材料固结装置的制造罐一起使用的表面层控制系统包括至少一个孔，其具有位于与制造槽内的未固结材料的期望表面水平大致相同的高度处的最下边缘。 表面水平控制系统还可以包括用于接收已经从制造罐移除的未固结材料的容器。 表面层控制系统可以被配置为不断地允许去除未固结的材料，或者可以将其配置为选择性地去除未固结的材料。 可以使用一个或多个传感器来监测表面水平并提供可用于将表面水平维持在基本恒定的高度的信息。 回收系统可以与表面层控制系统结合使用或与表面层控制系统分开使用，以将未固结的材料重新引入制造罐。

公开(公告)号：US20070020916A1

公开(公告)日：2007-01-25

申请号：US11184119

申请日：2005-07-19

申请人： Warren Farnworth

发明人： Warren Farnworth

IPC分类号： H01L23/58

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/243 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0367 ,  H05K2201/0373 ,  H01L2224/13099 ,  H01L2224/05099

摘要： A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they are all joined. The flexibility of the interconnect may be varied by controlling the column dimensions, height, aspect ratio, number of columns, column material and by applying a supporting layer of dielectric material to a controlled depth about the base of the columns. A large number of interconnects may be formed on a wafer, partial wafer, single die, interposer, circuit board, or other substrate.

摘要翻译： 用于微电子衬底的柔性柱互连件包括从接合焊盘或其它导电端子以基本上相互平行布置的方式延伸的多个导电柱，在接合焊盘和接触焊盘的形式的公共盖之间提供冗余的电流路径， 他们都加入了。 互连的灵活性可以通过控制柱尺寸，高度，纵横比，列数，柱材料以及通过将介电材料的支撑层施加到围绕柱的底部的受控深度来改变。 可以在晶片，部分晶片，单芯片，插入器，电路板或其它基板上形成大量互连。

公开(公告)号：US20070018336A1

公开(公告)日：2007-01-25

申请号：US11516097

申请日：2006-09-05

申请人： Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

发明人： Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/563 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2224/45099

摘要： Stress and force management techniques for a semiconductor die to help compensate for stress within the semiconductor die and to help compensate for forces applied to the semiconductor die to minimize damage thereto.

摘要翻译： 用于半导体管芯的应力和力管理技术来帮助补偿半导体管芯内的应力，并帮助补偿施加到半导体管芯上的力以最小化对其的损害。