公开(公告)号：US20050208781A1

公开(公告)日：2005-09-22

申请号：US10708735

申请日：2004-03-22

申请人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

发明人： John Fitzsimmons ,  Michael Lane ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper

IPC分类号： B05D1/02 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

摘要翻译： 形成方法和集成电路器件结构形成，具有与现有裂纹相邻的垂直接口围绕芯片的周边，由此垂直接口控制器件的侧面处理期间产生的裂纹，例如切割，并且在穿透裂纹停止 。 垂直界面由防止裂纹破坏裂纹的材料组成，通过使裂纹偏离穿透裂缝，或通过吸收所产生的裂纹能量来防止裂纹破裂。 或者，垂直界面可以是允许前进裂纹失去足够的能量使得它们不能穿透裂缝停止的材料。 现有的垂直接口可以以多种方式实现，例如释放材料的垂直间隔物，释放材料的垂直沟槽或释放材料的垂直通道。

公开(公告)号：US20050186689A1

公开(公告)日：2005-08-25

申请号：US10783462

申请日：2004-02-20

申请人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US06887783B2

公开(公告)日：2005-05-03

申请号：US10650890

申请日：2003-08-28

申请人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

发明人： Tze-Chiang Chen ,  Brett H. Engel ,  John A. Fitzsimmons ,  Terence Kane ,  Naftall E. Lustig ,  Ann McDonald ,  Vincent McGahay ,  Soon-Cheon Seo ,  Anthony K. Stamper ,  Yun Yu Wang ,  Erdem Kaltalioglu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由介电材料形成，优选沉积 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：US6133136A

公开(公告)日：2000-10-17

申请号：US314003

申请日：1999-05-19

申请人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

发明人： Daniel Charles Edelstein ,  Vincent McGahay ,  Henry A. Nye, III ,  Brian George Reid Ottey ,  William H. Price

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L23/485 ,  H01L21/4763

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L23/3192 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025

摘要： A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.

摘要翻译： 包括铜层，阻挡层，AlCu层和焊盘限制层的结构，其中AlCu层和阻挡层插入在铜层和焊盘限制层之间。

公开(公告)号：US20070072412A1

公开(公告)日：2007-03-29

申请号：US11162883

申请日：2005-09-27

申请人： Derren Dunn ,  Nicholas Fuller ,  Catherine Labelle ,  Vincent McGahay ,  Sanjay Mehta ,  Henry Nye III

发明人： Derren Dunn ,  Nicholas Fuller ,  Catherine Labelle ,  Vincent McGahay ,  Sanjay Mehta ,  Henry Nye III

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/31138 ,  H01L21/02118 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76831

摘要： Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.

摘要翻译： 通过在ILD中形成开口（例如，沟槽）来提供对层间电介质（ILD）的损坏的防止，并且通过在ILD内或在ILD内过度蚀刻到电介质层中，将电介质膜溅射到开口的侧壁上 形成开口。 再溅射的膜保护开口的侧壁不受后续的等离子体/灰分过程的影响，并且沿着侧壁和底部密封多孔电介质表面，而不影响整个工艺流程。 还公开了由上述方法得到的半导体结构。

公开(公告)号：US20060273460A1

公开(公告)日：2006-12-07

申请号：US11502196

申请日：2006-08-10

申请人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Jason Gill ,  Vincent McGahay ,  Paul McLaughlin ,  Conal Murray ,  Hazara Rathore ,  Thomas Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58 ,  H01L23/48 ,  H01L29/10 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US20060014376A1

公开(公告)日：2006-01-19

申请号：US11230841

申请日：2005-09-20

申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US06939797B2

公开(公告)日：2005-09-06

申请号：US10706773

申请日：2003-11-12

申请人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

发明人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

IPC分类号： H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/461

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

摘要翻译： 公开了一种先进的后端（BEOL）金属化结构。 该结构包括具有低介电常数（低-k）的扩散阻挡层或覆盖层，其中通过等离子体增强化学气相沉积（PE CVD）工艺，覆盖层由氮化硅形成。 金属化结构还包括由具有小于约4的介电常数的含碳电介质材料形成的层间电介质（ILD），以及优选由氮化硅或碳化硅形成的ILD上的连续硬掩模层。 还公开了一种用于形成BEOL金属化结构的方法。 该方法包括预清洁或预激活步骤，以改善盖层与下面的铜导体的粘合性。 预清洁或预活化步骤包括将铜表面暴露于包括氢，氨，氮和/或惰性气体的还原等离子体。

公开(公告)号：US06737747B2

公开(公告)日：2004-05-18

申请号：US10047965

申请日：2002-01-15

申请人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

发明人： Edward Barth ,  John A. Fitzsimmons ,  Stephen M. Gates ,  Thomas H. Ivers ,  Sarah L. Lane ,  Jia Lee ,  Ann McDonald ,  Vincent McGahay ,  Darryl D. Restaino

IPC分类号： H01L2348

CPC分类号： H01L21/76834 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

公开(公告)号：US20080020546A1

公开(公告)日：2008-01-24

申请号：US11862706

申请日：2007-09-27

申请人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

发明人： Edward COONEY ,  Vincent McGahay ,  Thomas Shaw ,  Anthony Stamper ,  Matthew Colburn

IPC分类号： H01L21/475 ,  H01L21/302 ,  H01L21/32 ,  H01L21/467

CPC分类号： H01L21/76829 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/78

摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.

摘要翻译： 本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。 可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。 粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。 可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。 用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。 然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。