公开(公告)号：US20140008819A1

公开(公告)日：2014-01-09

申请号：US13660249

申请日：2012-10-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/488 ,  H01L21/50 ,  B32B37/12 ,  H01L23/12

CPC classification number: H01L23/12 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  Y10T156/10 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A substrate structure is provided, including a substrate and a strengthening member bonded to a surface of the substrate. The strengthening member has a CTE (Coefficient of Thermal Expansion) less than that of the substrate so as to effectively prevent warpage from occurring to the substrate structure.

Abstract translation: 提供了一种基板结构，包括基板和结合到基板的表面的加强件。 加强构件具有小于衬底的CTE（热膨胀系数），以便有效地防止对衬底结构发生翘曲。

公开(公告)号：US20210296261A1

公开(公告)日：2021-09-23

申请号：US17337770

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20180254250A1

公开(公告)日：2018-09-06

申请号：US15624590

申请日：2017-06-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/06 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20170207161A1

公开(公告)日：2017-07-20

申请号：US15352856

申请日：2016-11-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US09548220B2

公开(公告)日：2017-01-17

申请号：US14986903

申请日：2016-01-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yi-Chian Liao ,  Yi-Che Lai

IPC: H01L21/48 ,  H01L21/58 ,  H01L23/498 ,  H01L21/78 ,  H01L23/00 ,  H01L23/14 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L21/486 ,  H01L21/31111 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49872 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/17 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/08235 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.

Abstract translation: 提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。 通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

公开(公告)号：US09515040B2

公开(公告)日：2016-12-06

申请号：US14736436

申请日：2015-06-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Chun-Tang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/18162

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract translation: 提供了一种制造封装结构的方法，包括以下步骤：在第一载体上依次形成金属层和电介质层，其中电介质层具有暴露金属层部分的多个开口; 将电子元件经由其活性表面设置在电介质层上，并将金属球的多个导电元件安装在金属层的暴露部分上; 在所述电介质层上形成密封剂以封装所述电子元件和所述导电元件; 移除第一载体; 以及将所述金属层图案化成第一电路并在所述电介质层上形成第二电路，其中所述第二电路电连接到所述电子元件和所述第一电路。 本发明省去了常规的激光烧蚀工艺，以简化制造工艺，节省制造成本并提高产品的可靠性。

公开(公告)号：US20160141281A1

公开(公告)日：2016-05-19

申请号：US14873445

申请日：2015-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US20160141227A1

公开(公告)日：2016-05-19

申请号：US14940554

申请日：2015-11-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chun-Tang Lin ,  Shih-Ching Chen ,  Yi-Che Lai ,  Hong-Da Chang ,  Hung-Wen Liu ,  Yi-Wei Liu ,  Hsi-Chang Hsu

IPC: H01L23/48 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.

Abstract translation: 提供一种制造封装结构的方法，其包括：提供其上具有电路层的第一载体; 在所述电路层上形成多个导电柱，并且至少在所述第一载体上布置电子元件; 在所述第一载体上形成密封剂以封装所述导电柱，所述电路层和所述电子元件; 并且移除第一载体，从而分配用于形成导电柱的传统开孔工艺，从而降低制造成本。

公开(公告)号：US09324582B2

公开(公告)日：2016-04-26

申请号：US13922798

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：在插入件上设置多个第一半导体元件; 在所述插入件上形成用于封装所述第一半导体元件的第一密封剂; 在所述第一半导体元件上设置多个第二半导体元件; 在所述第一半导体元件和所述第一密封剂上形成用于封装所述第二半导体元件的第二密封剂; 并使插入件变薄，从而减小整体堆叠厚度并防止插入件的翘曲。

公开(公告)号：US09224646B2

公开(公告)日：2015-12-29

申请号：US14146171

申请日：2014-01-02

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Hung-Wen Liu

IPC: H01L23/522 ,  H01L23/495 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76895 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract translation: 本发明公开了一种制造半导体封装的方法，包括提供具有绝缘层和至少嵌入绝缘层中的半导体元件的封装单元，其中半导体元件从绝缘层露出，并且形成在多个凹部中 绝缘层; 并且将再分布结构电连接到半导体元件。 凹陷部分的形成释放绝缘层的应力并防止绝缘层发生翘曲。