公开(公告)号：US09424928B2

公开(公告)日：2016-08-23

申请号：US14817281

申请日：2015-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-Jin Hwang ,  Pansuk Kwak ,  Younghwan Ryu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C5/025 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括在与衬底正交的方向上堆叠的单元串，并且包括分隔单元串的第一子串组和第二子串组以及经由单元串连接到单元串的存储单元的地址解码器 多个字线并且被配置为向存储器单元提供工作电压，其中地址解码器设置在第一子串组和第二子串组之间。

公开(公告)号：US12278182B2

公开(公告)日：2025-04-15

申请号：US17721481

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L23/528 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

公开(公告)号：US12002512B2

公开(公告)日：2024-06-04

申请号：US17709910

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08

Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

公开(公告)号：US11723208B2

公开(公告)日：2023-08-08

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Dongku Kang

IPC: G11C11/00 ,  H10B43/40 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  G11C7/18 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20230154559A1

公开(公告)日：2023-05-18

申请号：US18149302

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

IPC: G11C29/00 ,  G11C16/04 ,  G11C29/44 ,  G06F11/20

CPC classification number: G11C29/838 ,  G11C16/0483 ,  G11C29/44 ,  G06F11/2094 ,  G11C2029/1204

Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

公开(公告)号：US11574700B2

公开(公告)日：2023-02-07

申请号：US17245568

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

IPC: G11C29/00 ,  G06F11/20 ,  G11C16/04 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/12 ,  G11C29/02 ,  G11C29/52 ,  G11C29/42 ,  G11C29/24

Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

公开(公告)号：US11282851B2

公开(公告)日：2022-03-22

申请号：US16662073

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

公开(公告)号：US10381078B2

公开(公告)日：2019-08-13

申请号：US15992840

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dong-Kil Yun ,  Pansuk Kwak ,  Hongsoo Jeon

IPC: G11C14/00 ,  H01L27/11578 ,  H01L27/108 ,  H01L27/1157 ,  G11C11/4094 ,  G11C11/408 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/4091 ,  G11C16/04

Abstract: A semiconductor memory includes a first memory cell array in a first region of a substrate and a second memory cell array in a second region of the substrate. The first memory cell array includes cell strings, and each cell string includes non-volatile memory cells stacked in a direction perpendicular to the substrate. The second memory cell array includes volatile memory cells, and each volatile memory cell includes a select transistor and a capacitor. The capacitor includes at least one contact electrically connected with the select transistor and having a second height corresponding to a first height of each cell string, and at least one second contact supplied with a ground voltage, having a third height corresponding to the first height of each cell string, adjacent to the at least one first contact, and electrically disconnected with the at least one first contact.

公开(公告)号：US20250157496A1

公开(公告)日：2025-05-15

申请号：US18791587

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Changyeon Yu ,  Pansuk Kwak

IPC: G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a plurality of blocks each including a first substrate, a plurality of lower gate electrode layers stacked in a first direction perpendicular to an upper surface of the first substrate, a second substrate above the plurality of lower gate electrode layers, and a plurality of upper gate electrode layers stacked in the first direction on the second substrate; pass transistors electrically connected to the plurality of lower gate electrode layers and the plurality of upper gate electrode layers; and a row decoder electrically connected to the pass transistors, wherein a number of the plurality of lower gate electrode layers and a number of the plurality of upper gate electrode layers included in each of the plurality of blocks are greater than a number of the pass transistors.

公开(公告)号：US12249984B2

公开(公告)日：2025-03-11

申请号：US17886194

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

IPC: H01L27/02 ,  G06F1/26 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003

Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.