公开(公告)号：US11244904B2

公开(公告)日：2022-02-08

申请号：US16556538

申请日：2019-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-kwan Ryu ,  Yun-seok Choi

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region. The first semiconductor chip and the second semiconductor chip are mounted on the extension region and the interposer and disposed horizontally apart from each other. As seen from a plan view, the interposer is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US10008462B2

公开(公告)日：2018-06-26

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US09831202B2

公开(公告)日：2017-11-28

申请号：US15262040

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Ju-il Choi ,  Tae-je Cho ,  Yong-hwan Kwon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13564 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

公开(公告)号：US09666551B1

公开(公告)日：2017-05-30

申请号：US15236814

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Cha-jea Jo ,  Tae-Je Cho

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US20170084558A1

公开(公告)日：2017-03-23

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.