公开(公告)号：US20240404935A1

公开(公告)日：2024-12-05

申请号：US18662240

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Chae ,  Unbyoung Kang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a redistribution structure that includes a lower insulating layer, redistribution layers in the lower insulating layer, and first vias connected to the redistribution layers. The semiconductor package further includes a semiconductor chip on an upper surface of the redistribution structure and electrically connected to the redistribution layers; an interconnection structure on the upper surface of the redistribution structure and including an upper insulating layer, a plurality of interconnection layers, and second vias connecting the interconnection layers to each other; an encapsulant covering the semiconductor chip and the interconnection structure; and external connection conductors on a lower surface of the redistribution structure and electrically connected to the redistribution layers. A lowermost interconnection layer includes a first conductive layer contacting a second via and tapered toward the upper surface, and a second conductive layer surrounding the first conductive layer and in contact with a first via.

公开(公告)号：US20240321804A1

公开(公告)日：2024-09-26

申请号：US18489886

申请日：2023-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dowan Kim ,  Jieun Woo ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/2201 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package a first package unit comprising a semiconductor chip; and a redistribution structure on the first package unit, wherein the redistribution structure comprises a plurality of wiring lines and a plurality of insulating layers on the plurality of wiring lines, wherein the plurality of wiring lines comprise first subset including a plurality of outermost wiring lines and a second subset, wherein a vertical distance between the plurality of outermost wiring lines and the first package unit is greater than a vertical distance between the second subset of the plurality of wiring lines and the first package unit, a respective surface roughness of each of the plurality of outermost wiring lines is different, and the respective surface roughness of each of the plurality of outermost wiring lines is based on a respective width of each of the plurality of outermost wiring lines in a horizontal direction.

公开(公告)号：US20240321794A1

公开(公告)日：2024-09-26

申请号：US18679806

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US20240234103A1

公开(公告)日：2024-07-11

申请号：US18404423

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334

Abstract: A ring assembly is used in a semiconductor wafer etching device in which a plasma gas flow stream line is not uniform and which surrounds a wafer support plate supporting a semiconductor wafer. The ring assembly includes: an edge ring protruding from at least one side of the semiconductor wafer to have an upper surface higher than an upper surface of the semiconductor wafer; and a shadow ring movable up and down above the edge ring and configured to be tilted with respect to the semiconductor wafer.

公开(公告)号：US20230395403A1

公开(公告)日：2023-12-07

申请号：US18134718

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Myungsung Kang ,  Jaekyung Yoo ,  Unbyoung Kang ,  Chungsun Lee

IPC: H01L21/67

CPC classification number: H01L21/67126

Abstract: A molding apparatus for a semiconductor package includes a chamber including a lower mold configured to hold a substrate including a plurality of molding targets, an upper mold configured to move up and down with respect to the lower mold and define a cavity between the upper mold and the lower mold, and a port configured to provide a passage communicating with the cavity, a molding material supplier configured to supply a molding material to the port, a plunger configured to pressurize the molding material inside the port, a plunger actuator configured to apply a first pressure to the plunger such that the molding material provided in the port is supplied to the cavity, and a mold actuator configured to control actuation of the upper mold. The plunger actuator is configured to supply the molding material to the cavity by applying the first pressure to the plunger, and the mold actuator is configured to pressurize the molding material in the cavity by applying a second pressure to the upper mold. The mold apparatus further includes a controller configured to control the plunger actuator to reduce the first pressure applied to the plunger after the mold actuator begins applying the second pressure to the upper mold.

公开(公告)号：US11658141B2

公开(公告)日：2023-05-23

申请号：US17680477

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L22/22 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/481 ,  H01L2224/05124 ,  H01L2224/05564 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/08145 ,  H01L2224/2919 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/9211

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US11362062B2

公开(公告)日：2022-06-14

申请号：US17142133

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan Hwang ,  Unbyoung Kang ,  Sangsick Park ,  Jihwan Suh ,  Soyoun Lee ,  Teakhoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20220181285A1

公开(公告)日：2022-06-09

申请号：US17680477

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20210104482A1

公开(公告)日：2021-04-08

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/00 ,  H01L25/065

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20250079250A1

公开(公告)日：2025-03-06

申请号：US18810742

申请日：2024-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Kuyoung Kim

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a substrate structure, a plurality of semiconductor chips sequentially stacked on the substrate structure, a molding member on the substrate structure and surrounding side surfaces of the plurality of semiconductor chips, the molding member including a first material, and a first reforming portion in a side portion of the molding member, and extending horizontally in the side portion of the molding member to have a predetermined width from an outer side surface of the molding member. The first reforming portion may include a second material that is more brittle than the first material.