公开(公告)号：US08933336B2

公开(公告)日：2015-01-13

申请号：US13678033

申请日：2012-11-15

Applicant: TDK Corporation

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hideyuki Seike

IPC: H01B1/00 ,  H01B1/02

CPC classification number: H01B1/02 ,  H01L2224/85444

Abstract: A coating having a layered structure including a palladium layer is provided to a conductor. The highly stable palladium layer is amorphous and contains phosphorus in a concentration ranging from 7.3% by mass to 11.0% by mass. An electronic component may include the conductor coated with the coating. The conductor coated with the coating has superior corrosion resistance and superior reliability in electrical connection with external apparatuses.

Abstract translation: 具有包括钯层的层状结构的涂层被提供给导体。 高度稳定的钯层为无定形，含有浓度为7.3质量％〜11.0质量％的磷。 电子部件可以包括涂覆有涂层的导体。 涂覆有涂层的导体具有优异的耐腐蚀性和与外部设备电连接的优异的可靠性。

公开(公告)号：US11031330B2

公开(公告)日：2021-06-08

申请号：US16811018

申请日：2020-03-06

Applicant: TDK CORPORATION

Inventor： Takashi Daitoku ,  Susumu Taniguchi ,  Akiko Seki ,  Atsushi Sato ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hisayuki Abe

IPC: H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H01L21/48 ,  H05K3/40 ,  G06F3/044

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

公开(公告)号：US10354796B2

公开(公告)日：2019-07-16

申请号：US15840243

申请日：2017-12-13

Applicant: TDK Corporation

Inventor： Yuhei Horikawa ,  Makoto Orikasa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe ,  Hirohumi Asou ,  Kosuke Kunitsuka

IPC: H01F41/04 ,  H01F41/10 ,  C25D13/22 ,  C23C18/16 ,  C25D13/12 ,  G06K19/077 ,  H01Q1/38 ,  H01Q1/36 ,  H01Q9/27 ,  H05K3/24 ,  H05K3/18 ,  C25D5/48 ,  H01Q1/48 ,  H01Q7/00

Abstract: Disclosed herein is a method for manufacturing a planar coil, the method including forming a base conductive layer on a base material, the base conductive layer including: a coil wiring portion having one end, other end, and first to third connecting positions, the second connecting position being closer to the other end compared with the first connecting position, the third connecting position being closer to the one end compared with the second connecting position; a power-feed wiring portion that connects the first connecting position with an external power source; and a connection wiring portion that short-circuits the second connecting position and the third connecting position; forming a wiring conductive layer on the base conductive layer by electrolytic plating by feeding power from the external power source; and removing the power-feed wiring portion and the connection wiring portion.

公开(公告)号：US10205250B2

公开(公告)日：2019-02-12

申请号：US14219766

申请日：2014-03-19

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: B32B15/01 ,  H01R4/02 ,  B23K35/00 ,  H05K3/34 ,  H05K3/40 ,  H01L23/00

Abstract: A junction structure for electronic device having an excellent bonding strength is provided. A junction structure for electronic device in accordance with one aspect of the present invention includes a first metal layer containing nickel and a second metal layer containing gold, tin, and nickel, while the second metal layer includes an AuSn eutectic phase.

公开(公告)号：US09257402B2

公开(公告)日：2016-02-09

申请号：US13960330

申请日：2013-08-06

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Makoto Orikasa ,  Hideyuki Seike ,  Yuhei Horikawa ,  Hisayuki Abe

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.

Abstract translation: 优选的端子结构包括基材; 形成在基材上的电极; 绝缘覆盖层，形成在所述基底材料上和所述电极上，并且具有暴露所述电极的至少一部分的开口; 在所述电极的开口部的区域形成含有Ni的下凸块金属层，使得所述金属层的上表面位于比所述开口的周缘部的绝缘覆盖层的上表面低的位置; 以及形成在下凸块金属层的开口部的区域中的包含Sn和Ti的圆顶状的凸部，其中，下凸块状金属层与凸块之间的边界的端部与内凸块 绝缘覆盖层的开口部。

公开(公告)号：US09177687B2

公开(公告)日：2015-11-03

申请号：US13677509

申请日：2012-11-15

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hideyuki Seike

IPC: B32B15/01 ,  H01B1/02 ,  C22C5/04 ,  C23C18/16 ,  C23C18/00 ,  C25D3/00 ,  C25D5/00 ,  C23C18/34 ,  C23C18/44 ,  C23C18/54

CPC classification number: H01B1/026 ,  C22C5/04 ,  C23C18/1651 ,  C23C18/34 ,  C23C18/44 ,  C23C18/54 ,  H01B1/02 ,  Y10T428/12701 ,  Y10T428/12722 ,  Y10T428/12778 ,  Y10T428/12861 ,  Y10T428/12889 ,  Y10T428/12903

Abstract: A coating for a conductor, the coating having a layered structure of a palladium layer. The palladium layer has a crystal plane whose orientation rate is 65% or more, which means 65% or more of the crystal planes of the palladium layer are aligned to this crystal plane. Preferably the crystal plane whose orientation rate is 65% or more in the coating is the (111) plane or (200) plane.

Abstract translation: 一种用于导体的涂层，该涂层具有钯层的层状结构。 钯层具有取向率为65％以上的晶面，这意味着钯层的65％以上的晶面与该晶面对准。 优选地，涂层中取向率为65％以上的晶面是（111）面或（200）面。

公开(公告)号：US20130135834A1

公开(公告)日：2013-05-30

申请号：US13677432

申请日：2012-11-15

Applicant: TDK CORPORATION

Inventor： Yuhei Horikawa ,  Shin Fujita ,  Kenichi Yoshida ,  Hisayuki Abe ,  Makoto Orikasa ,  Hideyuki Seike

IPC: H05K1/11 ,  H01R43/00 ,  H01R4/02

CPC classification number: H05K1/11 ,  H01R4/02 ,  H01R43/00 ,  H05K1/111 ,  H05K1/141 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  Y02P70/613 ,  Y10T29/49204

Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.

Abstract translation: 电子设备包括端子结构和包括端子结构的印刷电路板。 端子结构包括放置在布线导体上的焊点导体区域，与导体区域接触的中间层以及与中间层接触的焊料区域。 中间层包括包含锡和铜和镍中的至少一种作为主要成分的金属间化合物。 当导体区域的压痕弹性模量为E1，中间层的压痕弹性模量为E2时，E1与E2的比例等于或大于0.8且等于或小于1.5。

公开(公告)号：US11869834B2

公开(公告)日：2024-01-09

申请号：US17314187

申请日：2021-05-07

Applicant: TDK CORPORATION

Inventor： Takashi Daitoku ,  Susumu Taniguchi ,  Akiko Seki ,  Atsushi Sato ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hisayuki Abe

IPC: H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H01L21/48 ,  H05K3/40 ,  G06F3/044

CPC classification number: H01L23/49838 ,  G06F3/044 ,  H01L21/4857 ,  H01L23/49866 ,  H01L33/62 ,  H05K1/09 ,  H05K3/4007 ,  H01L2933/0066 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/04

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

公开(公告)号：US11668008B2

公开(公告)日：2023-06-06

申请号：US17111040

申请日：2020-12-03

Applicant: TDK CORPORATION

Inventor： Makoto Orikasa ,  Yuhei Horikawa ,  Yoshihiro Kanbayashi ,  Hisayuki Abe

IPC: B32B27/08 ,  B32B27/36 ,  B32B15/09 ,  B32B15/20 ,  B32B3/30 ,  H01L23/52 ,  H01L27/15 ,  B32B27/18 ,  H01L23/498 ,  H01L33/62 ,  H01L23/14 ,  H01L25/075 ,  C23C18/16 ,  C23C18/32 ,  C23C18/38 ,  C23C18/30 ,  C23F1/02

CPC classification number: C23C18/1641 ,  B32B3/30 ,  B32B15/09 ,  B32B15/20 ,  B32B27/08 ,  B32B27/18 ,  B32B27/36 ,  C23C18/161 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  H01L23/52 ,  H01L27/156 ,  B32B2307/412 ,  B32B2457/20 ,  C23F1/02 ,  H01L23/145 ,  H01L23/498 ,  H01L25/0753 ,  H01L33/62

Abstract: A sheet material includes a resin layer containing a binder and catalyst particles, an electroless plating film on the side of one main surface of the resin layer and including first electroless plating films and a second electroless plating film, and a base material on the side of the other main surface of the resin layer.

公开(公告)号：US10392704B2

公开(公告)日：2019-08-27

申请号：US15415493

申请日：2017-01-25

Applicant: TDK CORPORATION

Inventor： Kenichi Yoshida ,  Yuhei Horikawa ,  Atsushi Sato ,  Hisayuki Abe

IPC: C23C18/42 ,  C23C18/16 ,  C23C18/32 ,  C23C18/54 ,  C23C28/02 ,  H01L23/00

Abstract: A method of providing a coating on a conductor. The coating has a first layer containing palladium and a second layer containing gold from the conductor side. The first layer has an inner layer on the conductor side and an outer layer arranged nearer to the second layer than the inner layer, and the outer layer has a higher phosphorus concentration than the inner layer.