公开(公告)号：US08912637B1

公开(公告)日：2014-12-16

申请号：US14034078

申请日：2013-09-23

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang

IPC: H01L21/78 ,  H01L23/495

CPC classification number: H01L24/70 ,  B82Y10/00 ,  B82Y40/00 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/0676 ,  H01L2224/27318 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29169 ,  H01L2224/29193 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/83385 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/01014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/207 ,  H01L2924/2075 ,  H01L2224/27 ,  H01L2924/00

Abstract: A method and apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.

Abstract translation: 一种有效提高半导体封装的热性能的方法和装置。 本发明的概念是在集成电路管芯的背面上提供硅纳米线，以直接将管芯附着于衬底，从而改善管芯与衬底之间的界面，从而通过提高粘合力来提高热性能和提高可靠性。

公开(公告)号：US12009280B2

公开(公告)日：2024-06-11

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US20230170282A1

公开(公告)日：2023-06-01

申请号：US17537923

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuntao Xu ,  Min Hui Ma ,  Tiange Xie ,  Rongwei Zhang

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/83 ,  H01L21/56 ,  H01L2224/32245 ,  H01L2224/32013 ,  H01L2224/73265 ,  H01L2224/8385

Abstract: A semiconductor device includes a silicon die having a first side and a second side, an adhesive layer attached to the first side of the silicon die, and a lead frame. The lead frame comprises a die attach pad having a mounting surface. The mounting surface has a smaller area than an area of the adhesive layer. The silicon die is mounted on the lead frame at the mounting surface so that edges of the silicon die and the adhesive layer overhang the die attach pad without touching the die attach pad. The semiconductor device further includes one or more leads that are spaced apart from the edges of the silicon die and the adhesive layer.

公开(公告)号：US20210050459A1

公开(公告)日：2021-02-18

申请号：US16539442

申请日：2019-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Alfred Kummerl ,  Simon Joshua Jacobs ,  James Richard Huckabee ,  Jo Bito ,  Rongwei Zhang

IPC: H01L31/0216 ,  H01L31/0203 ,  H01L31/02 ,  H01L23/00 ,  H01L31/024 ,  G02B5/20

Abstract: An integrated filter optical package including an ambient light sensor that incorporates an infrared (IR) filter in an integrated circuit (IC) stacked-die configuration is provided. The integrated filter optical package incorporates an infrared (IR) coated glass layer to filter out or block IR light while allowing visible (ambient) light to pass through to a light sensitive die having a light sensor. The ambient light sensor detects an amount of visible light that passes through the IR coated glass layer and adjusts a brightness or intensity of a display screen on an electronic device accordingly so that the display screen is readable.

公开(公告)号：US10559524B1

公开(公告)日：2020-02-11

申请号：US16133117

申请日：2018-09-17

Applicant: Texas Instruments Incorporated

Inventor： Sadia Naseem ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L21/00 ,  H01L29/00 ,  H01L23/12 ,  H01L23/495 ,  H01L23/64 ,  H01L23/00 ,  H01L21/56 ,  H01F27/28

Abstract: A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.

公开(公告)号：US10083896B1

公开(公告)日：2018-09-25

申请号：US15470486

申请日：2017-03-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Vikas Gupta

IPC: H01L21/50 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

公开(公告)号：US09780060B2

公开(公告)日：2017-10-03

申请号：US15368413

申请日：2016-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yong Lin ,  Vikas Gupta ,  Rongwei Zhang

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L24/29 ,  H01L21/304 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/544 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29034 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.

公开(公告)号：US20170053854A1

公开(公告)日：2017-02-23

申请号：US15346822

申请日：2016-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Yong Lin ,  Rongwei Zhang ,  Abram Castro ,  Matthew David Romig

IPC: H01L23/495 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/4952 ,  H01L21/2885 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/4867 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49883 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1511 ,  H01L2924/1711 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/0665

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract translation: 引线框架表面改性的方法包括提供至少一个预制金属引线框架或封装基板（基板）单元，其包括具有管芯焊盘和围绕管芯焊盘的多个接触区域的母材。 包括在固化步骤上形成固体的固体的材料或去除液体载体的烧结步骤的材料的油墨被加成沉积，其包括至少一个（i）芯片垫的区域 和（ii）在至少第一接触区域（第一接触区域）的一个区域。 油墨被烧结或固化以除去液体载体，使得残留基本上固体的油墨残余物。

公开(公告)号：US20160181183A1

公开(公告)日：2016-06-23

申请号：US14968234

申请日：2015-12-14

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  Abram Castro

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/562 ,  H01L24/03 ,  H01L24/04 ,  H01L24/26 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83862 ,  H01L2224/92247 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a pourous layer having a porosity of at least 10%; applying a die to said pourous layer; securing said die to said pourous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract translation: 本发明涉及一种用于抑制或防止在芯片附着/模具化合物与半导体器件的芯片焊盘和由这种方法形成的半导体器件的界面处的分层的方法。 该方法包括提供具有顶表面的引线框架; 用第一和第二硅烷涂层涂覆所述引线框架的所述顶表面; 加热所述硅烷涂层以形成孔隙率至少为10％的凹陷层; 将模具应用于所述薄层; 通过模具附着化合物将所述模具固定到所述多孔层; 并且在固着芯片附着材料和引线接合之后，通过成型施加模塑料。

公开(公告)号：US11018111B2

公开(公告)日：2021-05-25

申请号：US16423104

申请日：2019-05-27

Applicant: Texas Instruments Incorporated

Inventor： Rongwei Zhang ,  James Huckabee ,  Vikas Gupta

IPC: H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H01L21/304 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.