公开(公告)号：US11545513B2

公开(公告)日：2023-01-03

申请号：US17187955

申请日：2021-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Shyh-Fann Ting ,  Yen-Ting Chiang ,  Yeur-Luen Tu ,  Min-Ying Tsai

IPC: H01L27/146 ,  H04N5/365 ,  H01L21/762 ,  H01L31/0216

Abstract: In some embodiments, a method is provided. The method includes forming a plurality of trenches in a semiconductor substrate, where the trenches extend into the semiconductor substrate from a back-side of the semiconductor substrate. An epitaxial layer comprising a dopant is formed on lower surfaces of the trenches, sidewalls of the trenches, and the back-side of the semiconductor substrate, where the dopant has a first doping type. The dopant is driven into the semiconductor substrate to form a first doped region having the first doping type along the epitaxial layer, where the first doped region separates a second doped region having a second doping type opposite the first doping type from the sidewalls of the trenches and from the back-side of the semiconductor substrate. A dielectric layer is formed over the back-side of the semiconductor substrate, where the dielectric layer fill the trenches to form back-side deep trench isolation structures.

公开(公告)号：US20220037199A1

公开(公告)日：2022-02-03

申请号：US17232618

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Yu-Chun Chang ,  Ching I Li ,  Ru-Liang Lee

IPC: H01L21/762 ,  H01L27/12

Abstract: Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

公开(公告)号：US11171015B2

公开(公告)日：2021-11-09

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US20210126089A1

公开(公告)日：2021-04-29

申请号：US16663659

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Po-Wei Liu ,  Yeur-Luen Tu ,  Yu-Chun Chang

IPC: H01L29/06 ,  H01L21/763 ,  H01L21/762

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

公开(公告)号：US10569520B2

公开(公告)日：2020-02-25

申请号：US16220163

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Chen Tsao ,  Kuo Liang Lu ,  Ru-Liang Lee ,  Sheng-Hsiang Chuang ,  Yu-Hung Cheng ,  Yeur-Luen Tu ,  Cheng-Kang Hu

IPC: B32B38/10 ,  H01L21/67 ,  H01L21/68 ,  H01L21/683

Abstract: The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates diametrically opposite to each other. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly placed above the pair of bonded substrates and configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

公开(公告)号：US20200058746A1

公开(公告)日：2020-02-20

申请号：US16103101

申请日：2018-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Jiech-Fun Lu ,  Kuo-Hwa Tzeng ,  Shih-Pei Chou ,  Yu-Hung Cheng ,  Yeur-Luen Tu

IPC: H01L29/40 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L21/66 ,  H01L29/06

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

公开(公告)号：US20180350601A1

公开(公告)日：2018-12-06

申请号：US16043286

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chin Chen ,  Cheng-Yi Wu ,  Yu-Hung Cheng ,  Ren-Hua Guo ,  Hsiang Liu ,  Chin-Szu Lee

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/04 ,  H01L21/02

Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.

公开(公告)号：US09634096B2

公开(公告)日：2017-04-25

申请号：US14755990

申请日：2015-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/70 ,  H01L29/167 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

公开(公告)号：US09595589B2

公开(公告)日：2017-03-14

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L27/146 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US20150263123A1

公开(公告)日：2015-09-17

申请号：US14208905

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  I-Ting Li ,  Ming-Hsiang Kao

IPC: H01L29/51 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/42328 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

Abstract translation: 本公开涉及一种具有公共源极氧化物层的嵌入式闪存单元，其具有基本上平坦的顶表面，设置在公共源极区域和公共擦除栅极之间以及形成方法。 在一些实施例中，嵌入式闪存单元具有半导体衬底，其具有通过第一沟道区与第一漏极区分离的公共源极区，并且通过第二沟道区与第二漏极区分离。 通过原位蒸汽发生（ISSG）工艺在覆盖共同源极区域的位置形成高质量的共源氧化物层。 第一和第二浮栅设置在公共擦除栅极的相对侧上的第一和第二沟道区域上，该公共栅极具有与公共源极氧化物层的基本上平坦的顶表面邻接的基本平坦的底表面。