公开(公告)号：US07741196B2

公开(公告)日：2010-06-22

申请号：US11668453

申请日：2007-01-29

申请人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L21/30

CPC分类号： H01L21/3043 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

摘要翻译： 制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。 该结构布置成使得相邻的模具区域被用于切割工具的路径分开。 在每个路径中，制造一对间隔开的线。 每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。 每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

公开(公告)号：US09297713B2

公开(公告)日：2016-03-29

申请号：US14220121

申请日：2014-03-19

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/84 ,  G01L9/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

CPC分类号： G01L9/00 ,  G01L17/00 ,  G01L19/147 ,  G01L19/148 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/1624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014

摘要： A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost.

摘要翻译： 一种半导体压力传感器装置，其具有通过硅通孔（TSV）或倒装芯片凸块与微控制单元（MCU）电连接的压力感测管芯。 压敏传感芯片的有源表面与MCU面对关系。 这些实施例避免了使用键将电压连接到MCU的需要，从而节省时间，减小尺寸并降低成本。

公开(公告)号：US08378435B2

公开(公告)日：2013-02-19

申请号：US12960571

申请日：2010-12-06

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L24/97 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of packaging a pressure sensing die includes providing a lead frame with lead fingers and attaching the pressure sensing die to the lead fingers such that bond pads of the die are electrically coupled to the lead fingers and a void is formed between the die and the lead fingers. A gel material is dispensed via an underside of the lead frame into the void such that the gel material substantially fills the void. The gel material is then cured and the die and the lead frame are encapsulated with a mold compound. The finished package does not include a metal lid.

摘要翻译： 一种包装压力传感管芯的方法包括提供具有引线指状物的引线框架并将压力感测裸片连接到引线指，使得管芯的接合焊盘电连接到引线指，并且在管芯和管芯之间形成空隙 铅笔指 凝胶材料通过引线框架的下侧分配到空隙中，使得凝胶材料基本上填充空隙。 然后将凝胶材料固化，并将模具和引线框架用模具化合物包封。 成品包装不包括金属盖。

公开(公告)号：US20080179710A1

公开(公告)日：2008-07-31

申请号：US11668453

申请日：2007-01-29

申请人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L21/3043 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

摘要翻译： 制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。 该组合被布置成使得相邻的模具区域被用于每个路径内的切割工具的路径分开，制造一对间隔开的线。 每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。 每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

公开(公告)号：US09589928B2

公开(公告)日：2017-03-07

申请号：US14552497

申请日：2014-11-25

申请人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

发明人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

摘要翻译： 半导体封装包括具有第一类型的封装引线和预成型部分的第一引线框架型和具有围绕芯片焊盘并由预模制部分支撑的第二类型的封装引线的第二引线框架型 。 集成电路附接到管芯焊盘并且用接合线电连接到第一和第二类型的引线。 形成模具帽的模具复合体覆盖第一和第二引线框架类型，集成电路和接合线。 第一引线框类型可以是QFP型，第二引线框类型可以是QFN型。

公开(公告)号：US20150097278A1

公开(公告)日：2015-04-09

申请号：US14459328

申请日：2014-08-14

申请人： Zhigang Bai ,  Yin Kheng Au ,  Lan Chu Tan ,  Jinzhong Yao

发明人： Zhigang Bai ,  Yin Kheng Au ,  Lan Chu Tan ,  Jinzhong Yao

IPC分类号： H01L23/495

CPC分类号： H01L21/4842 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

摘要： Assembling a surface mount semiconductor device includes providing a lead frame structure with peripheral leads and additional bottom face contacts integral with frame members. Outer portions of the bottom face contact members are interposed between inner portions of adjacent pairs of the peripheral leads. A package body is formed by encapsulating the lead frame structure in which the frame members are positioned outside a side edge surface. The peripheral leads and the bottom face contact members project between the side edge surface of the package body and the frame members. The frame members are cut and the peripheral leads and the bottom face contact members are separated and electrically isolated from each other.

摘要翻译： 组装表面贴装半导体器件包括提供具有周边引线的引线框结构和与框架构件一体的附加底面接触。 底面接触构件的外部部分位于相邻的外围引线对的内部之间。 通过封装框架构件定位在侧边缘表面外侧的引线框架结构形成封装体。 外围引线和底面接触构件在封装主体的侧边缘表面和框架构件之间突出。 框架构件被切割，并且周边引线和底面接触构件彼此分离并电隔离。

公开(公告)号：US20150294924A1

公开(公告)日：2015-10-15

申请号：US14552497

申请日：2014-11-25

申请人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

发明人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

摘要翻译： 半导体封装包括具有第一类型的封装引线和预成型部分的第一引线框架型和具有围绕芯片焊盘并由预模制部分支撑的第二类型的封装引线的第二引线框架型 。 集成电路附接到管芯焊盘并且用接合线电连接到第一和第二类型的引线。 形成模具帽的模具复合体覆盖第一和第二引线框架类型，集成电路和接合线。 第一引线框类型可以是QFP型，第二引线框类型可以是QFN型。

公开(公告)号：US20160064356A1

公开(公告)日：2016-03-03

申请号：US14474294

申请日：2014-09-01

申请人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/03602 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L21/565 ,  H01L21/304 ,  H01L2224/83

摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。

公开(公告)号：US08853058B2

公开(公告)日：2014-10-07

申请号：US13530117

申请日：2012-06-22

申请人： Kesvakumar V. C. Muniandy ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Kesvakumar V. C. Muniandy ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L21/568 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/3735 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00

摘要： A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

摘要翻译： 一种组装半导体器件的方法包括提供一种结构，其包括除了孔阵列之外的导电框架构件的阵列和在第一面处暴露并朝向第二面延伸的导电通孔阵列。 一组半导体管芯位于孔阵列中，其主动面位于结构的第一面。 组件从结构的第二面被封装，并且在结构的第一面和模具的有效面上形成再分布层。 从封装阵列的背面去除材料以暴露在背面的通孔，用于通过形成在背面上的另一重新分配层与垂直堆叠在再分布层上的电子部件连接。

公开(公告)号：US20070281393A1

公开(公告)日：2007-12-06

申请号：US11421006

申请日：2006-05-30

申请人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

发明人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of forming a semiconductor package (32) includes etching a conductive sheet (10) to form a first interconnection system (12). An integrated circuit (IC) die (22) is placed on and electrically connected to the first interconnection system (12). Next, a molding operation is performed to encapsulate the IC die (22), the electrical connections (24, 26) and at least a portion of the first interconnection system (12). A portion (20) of the conductive sheet (10) is then removed to expose a surface (30) of the first interconnection system (12). A second interconnection system (34) then is formed over the exposed surface (30) of the first interconnection system (12).

摘要翻译： 形成半导体封装（32）的方法包括蚀刻导电片（10）以形成第一互连系统（12）。 集成电路（IC）管芯（22）放置在电连接到第一互连系统（12）上。 接下来，执行模制操作以封装IC管芯（22），电连接（24,26）和第一互连系统（12）的至少一部分。 然后去除导电片（10）的一部分（20）以暴露第一互连系统（12）的表面（30）。 然后在第一互连系统（12）的暴露表面（30）上形成第二互连系统（34）。