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公开(公告)号：US11620500B2
公开(公告)日：2023-04-04
申请号：US15868392
申请日：2018-01-11
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Chih-Cheng Fu , Ming-Che Lin , Yu-Ting Chen , Seow-Fong (Dennis) Lim
Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
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公开(公告)号：US11520526B2
公开(公告)日：2022-12-06
申请号：US17337003
申请日：2021-06-02
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Chien-Min Wu , Chia Hua Ho , Frederick Chen , He-Hsuan Chao , Seow-Fong Lim
Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.
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公开(公告)号：US20220069209A1
公开(公告)日：2022-03-03
申请号：US17002759
申请日：2020-08-25
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Chia-Wen Cheng , He-Hsuan Chao , Frederick Chen , Chang-Tsung Pai , Tzu-Yun Huang , Ming-Che Lin
Abstract: A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.
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公开(公告)号：US10978336B2
公开(公告)日：2021-04-13
申请号：US16704152
申请日：2019-12-05
Applicant: Winbond Electronics Corp.
Inventor： Cheng-Hui Tu , Chi-Ching Liu , Ting-Ying Shen , Yen-De Lee , Ping-Kun Wang
IPC: H01L21/768
Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
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公开(公告)号：US20190221260A1
公开(公告)日：2019-07-18
申请号：US16181372
申请日：2018-11-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Yu-Ting Chen , Ming-Che Lin , Chien-Min Wu , Chia-Hua Ho
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C2013/0045
Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20180366197A1
公开(公告)日：2018-12-20
申请号：US15997717
申请日：2018-06-05
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Shao-Ching Liao , Ming-Che Lin , Min-Chih Wei , Chuan-Sheng Chou
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/52 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/146 , H01L45/147
Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.
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公开(公告)号：US20170117038A1
公开(公告)日：2017-04-27
申请号：US14918574
申请日：2015-10-21
Applicant: Winbond Electronics Corp.
Inventor： Shao-Ching Liao , Ping-Kun Wang , Frederick Chen
IPC: G11C13/00
CPC classification number: G11C11/00 , G11C5/147 , G11C11/5642 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , H01L27/2409 , H01L45/00
Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.
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公开(公告)号：US09496036B1
公开(公告)日：2016-11-15
申请号：US14953447
申请日：2015-11-30
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Shao-Ching Liao , Pei-Hsiang Liao
CPC classification number: G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/009 , G11C2013/0092 , G11C2213/79 , G11C2213/82
Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.
Abstract translation: 提供了一种用于电阻式存储单元和电阻式存储器的写入方法。 写作方法包括以下步骤。 参考电压被提供给电阻存储单元的位线。 第一电压被提供给电阻存储单元的字线，并且第二电压被提供给电阻存储单元的源极线，其中第一电压不增加，而第二电压逐渐增加。 因此，当执行电阻性存储单元的写入方法时，在线源的电压逐渐增加的同时，字线的电压不增加，从而扩大用于复位操作的电压窗口。 并且，由于过大的输入电压而发生电阻式存储单元的互补切换表现的机会降低。
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公开(公告)号：US20240087644A1
公开(公告)日：2024-03-14
申请号：US18457377
申请日：2023-08-29
Applicant: Winbond Electronics Corp.
Inventor： I-Hsien Tseng , Lung-Chi Cheng , Ju-Chieh Cheng , Jun-Yao Huang , Ping-Kun Wang
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0007 , G11C2013/0083
Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.
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公开(公告)号：US11289157B1
公开(公告)日：2022-03-29
申请号：US17012077
申请日：2020-09-04
Applicant: Winbond Electronics Corp.
Inventor： Frederick Chen , Ping-Kun Wang , Kuang-Chih Hsieh , Chien-Min Wu , Meng-Hung Lin
Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.
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