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    Chip package and method of manufacturing the same
    11.
    发明授权
    Chip package and method of manufacturing the same 有权
    芯片封装及其制造方法

    公开(公告)号：US09269837B2

    公开(公告)日：2016-02-23

    申请号：US14682888

    申请日：2015-04-09

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

    IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

    CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

    Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

    Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

    Semiconductor package and fabrication method thereof
    14.
    发明授权
    Semiconductor package and fabrication method thereof 有权
    半导体封装及其制造方法

    公开(公告)号：US08928098B2

    公开(公告)日：2015-01-06

    申请号：US13714218

    申请日：2012-12-13

    Applicant: Xintec Inc.

    Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

    Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

    Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

    Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region
    15.
    发明授权
    Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region 有权

    公开(公告)号：US12272712B2

    公开(公告)日：2025-04-08

    申请号：US17744664

    申请日：2022-05-14

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

    IPC: H01L21/48 ,  H01L27/146

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

    Chip package and method for forming the same
    16.
    发明授权
    Chip package and method for forming the same 有权

    公开(公告)号：US12237354B2

    公开(公告)日：2025-02-25

    申请号：US17683917

    申请日：2022-03-01

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Chaung-Lin Lai

    IPC: H01L27/146

    Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

    Manufacturing method of chip package and chip package
    17.
    发明授权
    Manufacturing method of chip package and chip package 有权

    公开(公告)号：US11942563B1

    公开(公告)日：2024-03-26

    申请号：US18327875

    申请日：2023-06-01

    Applicant: XINTEC INC.

    Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC: H01L31/0352 ,  H01L31/02

    CPC classification number: H01L31/03529 ,  H01L31/02005

    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

    Manufacturing method of chip package
    19.
    发明授权
    Manufacturing method of chip package 有权

    公开(公告)号：US11476293B2

    公开(公告)日：2022-10-18

    申请号：US16950810

    申请日：2020-11-17

    Applicant: XINTEC INC.

    Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Po-Han Lee

    IPC: H01L27/146 ,  H01L23/00

    Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

    MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE
    20.
    发明申请
    MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE 有权

    公开(公告)号：US20210343591A1

    公开(公告)日：2021-11-04

    申请号：US17373773

    申请日：2021-07-13

    Applicant: XINTEC INC.

    Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/02

    Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

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