公开(公告)号：US11776964B2

公开(公告)日：2023-10-03

申请号：US16691730

申请日：2019-11-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki

IPC: H01L27/105 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/12 ,  G11C11/405 ,  G11C16/04 ,  H01L21/8258 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207 ,  H01L28/60 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11728406B2

公开(公告)日：2023-08-15

申请号：US17121343

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/3205 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/0262 ,  H01L21/02359 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02645 ,  H01L21/02664 ,  H01L21/32055 ,  H01L21/32137 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US11697889B2

公开(公告)日：2023-07-11

申请号：US16719088

申请日：2019-12-18

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Keith E. Fogel

IPC: C30B29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L21/683 ,  H01L21/02 ,  H01L23/498 ,  C30B25/18 ,  C30B33/06 ,  C30B29/64 ,  H01L21/18 ,  C30B29/52 ,  B32B3/30 ,  B23B3/30 ,  B32B3/28

CPC classification number: C30B29/06 ,  B23B3/30 ,  B32B3/28 ,  B32B3/30 ,  C30B25/18 ,  C30B29/52 ,  C30B29/64 ,  C30B33/06 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02433 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02664 ,  H01L21/185 ,  H01L21/6835 ,  H01L23/4985 ,  H01L29/04 ,  H01L29/0657 ,  H01L29/16 ,  H01L21/02598 ,  H01L2221/68345 ,  H01L2221/68381

Abstract: A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

公开(公告)号：US11658028B2

公开(公告)日：2023-05-23

申请号：US16539157

申请日：2019-08-13

Applicant: TOKYO ELECTRON LIMITED

Inventor： Rui Kanemura ,  Hiroyuki Hayashi

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  C23C16/24 ,  C23C16/56 ,  C23C16/52

CPC classification number: H01L21/02532 ,  C23C16/24 ,  C23C16/52 ,  C23C16/56 ,  H01L21/0262 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/3065 ,  H01L21/67069

Abstract: A film forming method for forming a silicon film having a step coverage on a substrate having a recess in a surface of the substrate, the film forming method comprising: forming a silicon film such that a film thickness on an upper portion of a side wall of the recess is thicker than a film thickness on a lower portion of the side wall of the recess by supplying a silicon-containing gas to the substrate; and etching a portion of the silicon film conformally by supplying an etching gas to the substrate, wherein the act of forming the silicon film and the act of etching the portion of the silicon film are performed a number of times which is determined depending on the step coverage.

公开(公告)号：US20190122886A1

公开(公告)日：2019-04-25

申请号：US15879608

申请日：2018-01-25

Applicant: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.O.C.

Inventor： DER-JUN JAN ,  Shih-Shou Lo ,  Cheng-How Wang

IPC: C09C1/04 ,  H01L21/02 ,  B82Y40/00 ,  B82Y30/00

CPC classification number: H01L21/02606 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02172 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02664 ,  H01L35/16 ,  H01L35/26

Abstract: A method for manufacturing a nanostructure composite material includes a step of preparing an inorganic material nanostructure, and a step of embedding an organic material to the inorganic material nanostructure so as to form the nanostructure composite material. In addition, a nanostructure composite material is also provided.

公开(公告)号：US20190088495A1

公开(公告)日：2019-03-21

申请号：US16044479

申请日：2018-07-24

Applicant: MICROLINK DEVICES, INC.

Inventor： Christopher Youtsey ,  Robert McCarthy ,  Rekha Reddy

IPC: H01L21/306 ,  H01L21/67 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L21/30612 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30635 ,  H01L21/67075 ,  H01L21/67086 ,  H01L21/78 ,  H01L21/7813 ,  H01L29/2003 ,  H01L31/02363 ,  H01L33/0075 ,  H01L33/22

Abstract: Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.

公开(公告)号：US20190043714A1

公开(公告)日：2019-02-07

申请号：US15997939

申请日：2018-06-05

Applicant: International Business Machines Corporation

Inventor： Yun Seog LEE ,  Talia S. GERSHON ,  Joel P. DE SOUZA ,  Devendra K. SADANA

IPC: H01L21/02 ,  H01L29/20

CPC classification number: H01L21/02312 ,  H01L21/02052 ,  H01L21/02304 ,  H01L21/02546 ,  H01L21/02664 ,  H01L21/28264 ,  H01L21/306 ,  H01L21/67207 ,  H01L29/20 ,  H01L29/513

Abstract: A semiconductor structure, a method, and an apparatus for in-situ sulfur vapor passivation of an interface surface of an indium gallium arsenide layer of the semiconductor structure. A method includes elemental sulfur-vapor passivation of an interface surface of an indium gallium arsenide layer disposed on a substrate. A dielectric layer can be deposited on the sulfur-vapor passivated interface surface. An annealing process can be performed after the deposition of the dielectric layer. The annealing process anneals the indium gallium arsenide layer including the sulfur-vapor passivated interface surface and the dielectric layer disposed on the sulfur-vapor passivated interface surface. The sulfur-vapor passivation, the deposition of the dielectric layer, and the anneal, can be performed in-situ in a vacuum chamber without breaking a vacuum of the vacuum chamber following a III-V material growth process in the vacuum chamber to form the indium gallium arsenide layer.

公开(公告)号：US20190027513A1

公开(公告)日：2019-01-24

申请号：US15575054

申请日：2017-08-01

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY

Inventor： Leilei Dong

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/1274 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/3065 ,  H01L21/32115 ,  H01L27/1222 ,  H01L27/3262 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

Abstract: The present disclosure discloses a manufacturing method of a polycrystalline silicon thin film, which includes: forming a first amorphous silicon thin film; crystallizing the first amorphous silicon thin film to form a polycrystalline silicon thin film by applying an excimer laser annealing process; forming a second amorphous silicon thin film on a first surface of the polycrystalline silicon thin film; and etching until the second amorphous silicon thin film is completely removed toward a direction of the polycrystalline silicon thin film from the second amorphous silicon thin film by applying a dry etching process. The present disclosure further discloses a manufacturing method of a thin film transistor array substrate which includes the steps of manufacturing an active layer: forming a layer of a polycrystalline silicon thin film according to the previous polycrystalline silicon thin film; and etching the polycrystalline silicon thin film to form a patterned active layer.

公开(公告)号：US10074517B2

公开(公告)日：2018-09-11

申请号：US13543796

申请日：2012-07-07

Applicant: Nobuyuki Kuboi ,  Masanaga Fukusawa

Inventor： Nobuyuki Kuboi ,  Masanaga Fukusawa

IPC: H01L21/30 ,  H01J37/32 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01J37/32082 ,  H01L21/02041 ,  H01L21/02043 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/02664 ,  H01L21/28185

Abstract: A plasma treatment method includes: creating a plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor substrate with the CN active species.

公开(公告)号：US20180254185A1

公开(公告)日：2018-09-06

申请号：US15905359

申请日：2018-02-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Mohammed Benwadih ,  Christine Revenant-Brizard

IPC: H01L21/02 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L21/02628 ,  H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02502 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02664 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

Abstract: The present application relates to a method for forming an active zone of metal oxide for an electronic component including the formation of a stack of IXZO layers produced by liquid phase deposition on a substrate, the layers of said stack having different atomic fractions to each other in order to make it possible to reduce the annealing temperature enabling them to be made functional.