公开(公告)号：US20020095785A1

公开(公告)日：2002-07-25

申请号：US10011405

申请日：2001-12-11

发明人： Shinsaku Kubo ,  Kazuya Ishiwata ,  Yoshimi Uda ,  Yasuyuki Watanabe ,  Hiroaki Toshima

IPC分类号： H05K003/10

CPC分类号： H01J9/027 ,  H01J9/185 ,  H05K3/4664 ,  Y10T29/49155

摘要： The wirings on an electron source substrate are formed to intersect with each other in a matrix so as to address the electron emission devices on the substrate. First and second wirings intersect with each other on a crossing point. As such a crossing point, an insulating layer is placed between the first and second wirings. To ensure insulation, a plurality of insulating layers are laminated. According to the present invention, a wiring pattern is provided on the substrate with a conductive paste and baking the wiring pattern of the conductive paste to form the first wiring. Subsequently part of the first wiring is coated at the crossing point with an insulating paste and baking the insulating paste to form a first insulating layer. The coating thickness of the insulating layer formed adjacent to sidewalls of the crossing point is substanially equal to the height of the first wiring.

摘要翻译： 电子源基板上的布线形成为以矩阵相互交叉，以便寻址基板上的电子发射器件。 第一和第二布线在交叉点处彼此相交。 作为这样的交叉点，绝缘层被放置在第一和第二布线之间。 为了确保绝缘，层叠多个绝缘层。 根据本发明，通过导电膏在基板上设置布线图案，并烘烤导电浆料的布线图形，形成第一布线。 随后，第一布线的一部分在交叉点用绝缘膏涂覆并烘烤绝缘膏以形成第一绝缘层。 与交叉点的侧壁相邻形成的绝缘层的涂层厚度基本等于第一布线的高度。

公开(公告)号：US20020079133A1

公开(公告)日：2002-06-27

申请号：US10059222

申请日：2002-01-31

申请人： Mitsui Mining & Smelting Co. Ltd.

发明人： Takuya Yamamoto ,  Takashi Kataoka ,  Yutaka Hirasawa ,  Naotomi Takahashi

IPC分类号： H05K001/03 ,  H05K001/09 ,  H05K003/10 ,  H05K003/20

CPC分类号： H05K3/025 ,  H05K3/108 ,  H05K3/384 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/12028 ,  Y10T428/12438 ,  Y10T428/12493 ,  Y10T428/12646 ,  Y10T428/12715 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/265 ,  Y10T428/2839

摘要： This invention aims at providing metal foil and an etching process which can overcome the problem exists on the conventional semi-additive process for producing printed wiring boards, the problem being such that not only the copper foil layer but also the plating copper layer formed on a metal clad laminate is etched and thereby the edge portion of the circuit is attacked during the flash etching carried out in the final step of the production process. In light of the above problem, the metal foil and the metal foil with carrier foil of this invention are characterized in that a nickel or tin layer 0.5 to 3 nullm thick can be formed on the external surface of the metal clad laminate. And the semi-additive process for producing printed wiring boards of this invention is characterized in that it includes the steps of: forming a metal clad laminate using the copper foil or metal foil with carrier foil of this invention; forming a plating resist layer on the nickel or tin layer; removing the plating resist layer of a circuit formed portion while leaving the plating resist layer of a circuit unformed portion alone by subjecting the plating resist layer to circuit forming pattern exposure and development; forming a plated copper layer on the nickel or tin layer of the circuit formed portion by pattern copper plating; removing the plating resist layer of the circuit unformed portion; and removing the nickel or tin layer of the circuit unformed portion alone by the flash etching process using a selective etchant which allows the copper layer to remain undissolved.

摘要翻译： 本发明的目的在于提供金属箔和蚀刻工艺，其可以克服用于制造印刷电路板的常规半加成工艺存在的问题，不仅铜箔层而且镀铜层形成在 蚀刻金属箔层压体，由此在生产过程的最后步骤中进行的闪光蚀刻期间电路的边缘部分受到攻击。 鉴于上述问题，本发明的金属箔和带有载体箔的金属箔的特征在于，可以在覆金属层压板的外表面上形成0.5-3μm厚的镍或锡层。 本发明的印刷线路板的半添加方法的特征在于，包括以下步骤：使用本发明的载体箔的铜箔或金属箔形成覆金属层压体; 在镍或锡层上形成电镀抗蚀剂层; 除去电路形成部分的电镀抗蚀剂层，同时通过对电镀抗蚀剂层进行电路形成图案曝光和显影而单独留下电路未成形部分的电镀抗蚀剂层; 通过图案镀铜在电路形成部分的镍或锡层上形成镀覆铜层; 去除电路未成形部分的电镀抗蚀剂层; 并且通过使用允许铜层保持未溶解的选择性蚀刻剂的闪光蚀刻工艺单独除去电路未成形部分的镍或锡层。

公开(公告)号：US20020023344A1

公开(公告)日：2002-02-28

申请号：US09940655

申请日：2001-08-29

发明人： Kazuhide Ohira ,  Teturou Uchida

IPC分类号： H05K003/02 ,  H05K003/10 ,  B23P017/00

CPC分类号： H05K3/0052 ,  H05K1/0286 ,  H05K2201/09063 ,  H05K2201/0909 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49789

摘要： A method for manufacturing two kinds of printed circuit boards from one master board, comprises the steps of preparing the master board, forming slits on the master board to define a first circuit area, and executing: (a) forming first cut grooves extending substantially perpendicular to the slits so as to across outer side of both ends of the slits on the master board to define a second circuit area which surrounds the first circuit area, and cutting the master board along the first cut grooves to separate a first individual circuit board including the first and second circuit areas, or (b) forming second cut grooves on the master board so as to across both ends of the slits, and cutting the master board along the second cut grooves to separate a second individual circuit board including only the first circuit area.

摘要翻译： 一种用于从一个主板制造两种印刷电路板的方法包括以下步骤：准备主板，在主板上形成狭缝以限定第一电路区域，并执行：（a）形成基本垂直延伸的第一切割槽 到所述狭缝，以便跨越所述主板上的狭缝的两端的外侧，以限定围绕所述第一电路区域的第二电路区域，以及沿着所述第一切割槽切割所述主板，以分离第一单独电路板，所述第一单独电路板包括 第一和第二电路区域，或（b）在主板上形成第二切割凹槽以跨过狭缝的两端，并沿着第二切割槽切割主板，以分离仅包括第一切割槽的第二单独电路板 电路面积。

公开(公告)号：US20010042304A1

公开(公告)日：2001-11-22

申请号：US09919107

申请日：2001-07-31

发明人： Kiyoshi Sato

IPC分类号： H05K003/10 ,  H05K003/20

CPC分类号： G11B5/3103 ,  G11B5/3106 ,  G11B5/3163 ,  G11B5/3967 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/244 ,  H05K3/4007 ,  H05K3/4038 ,  Y10T29/49128 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2924/00

摘要： In a thin-film structure, since a flat face of a bump, which is exposed at the surface of an insulating layer and is to be in contact with an electrode layer, is an exposed surface of a nickel layer, an oxide layer on the flat face can be reliably removed by using ion-milling or sputter etching.

摘要翻译： 在薄膜结构中，由于在绝缘层的表面露出并与电极层接触的突起的平坦面是镍层的露出面，所以在 可以通过使用离子铣削或溅射蚀刻可靠地去除平坦的表面。

公开(公告)号：US20040244191A1

公开(公告)日：2004-12-09

申请号：US10492153

申请日：2004-04-09

发明人： Bruce Orr ,  Brett Sexton

IPC分类号： H05K003/10

CPC分类号： H05K3/4092 ,  Y10T29/49147 ,  Y10T29/49155

摘要： A method of fabricating electromechanical devices such as micro relays on printed circuit boards. The method includes the deposition of an element of the component onto an electrically conducting sacrificial layer, which is subsequently removed to form a PCB component that is suspended above the PCB substrate. In one embodiment, the vias in a multilayer PCB are used as the anchor posts for the suspended component.

摘要翻译： 在印刷电路板上制造诸如微型继电器之类的机电装置的方法。 该方法包括将元件的元件沉积到导电牺牲层上，随后将其移除以形成悬挂在PCB衬底上的PCB元件。 在一个实施例中，多层PCB中的通孔用作悬挂部件的锚固柱。

公开(公告)号：US20040168314A1

公开(公告)日：2004-09-02

申请号：US10667825

申请日：2003-09-22

发明人： Giuseppe Pedretti ,  Ken Varley

IPC分类号： H05K003/00 ,  H05K003/02 ,  H05K003/10

CPC分类号： H05K1/0265 ,  H05K3/062 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/0355 ,  H05K2201/09736 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A process of manufacturing printed circuit boards which is useful in the formation of printed circuit boards containing both areas of thick conductive traces and areas of fine resolution conductors in a single conductive layer, and printed circuit boards formed from such a process. A conductive core is first fabricated containing areas of thick conductors on a relatively thin conductive base. The conductive core is then bonded to a sublayer such as nullprepregnull with the thick conductive areas adjacent to the sublayer in order to form a relatively flat laminate. Proper bonding typically requires the use of high resin nullprepregnull sublayer. In the alternative, an additional inner layer of pure resin can be inserted between the conductive core and the insulating sublayer prior to bonding. After bonding, the conductive surface of the laminate is formed into printed conductor traces by methods known in the art. For example, chemical etching may be used to remove conductive material not comprising the printed circuits. In various embodiments of the invention a solder mask coating is applied to the completed printed circuit board. By use of this process, a single layer printed circuit comprising both thick conductor traces and fine resolution traces is possible. This invention is also useful in manufacturing a printed circuit core or layer suitable for use as a component in a multilayer printed circuit board where it is desirable that a relative flat layer containing thick conductor traces be provided.

摘要翻译： 制造印刷电路板的方法，其可用于形成在单个导电层中包含厚导电迹线和精细分辨率导体的区域的印刷电路板，以及由这种方法形成的印刷电路板。 首先制造导电芯，其在相对薄的导电基底上包含厚导体区域。 然后将导电芯结合到诸如“半固化片”之类的子层，其中厚的导电区域邻近子层，以形成相对平坦的层压体。 适当的粘合通常需要使用高树脂“预浸料”子层。 替代地，在粘合之前，可以在导电芯和绝缘子层之间插入额外的纯树脂内层。 在粘合之后，层压体的导电表面通过本领域已知的方法形成印刷导体迹线。 例如，可以使用化学蚀刻来去除不包括印刷电路的导电材料。 在本发明的各种实施例中，将焊接掩模涂层施加到完成的印刷电路板。 通过使用该工艺，可以使用包括厚导体迹线和精细分辨率迹线的单层印刷电路。 本发明也可用于制造适合用作多层印刷电路板中的组件的印刷电路芯或层，其中期望提供包含厚导体迹线的相对平坦层。

公开(公告)号：US20040163247A1

公开(公告)日：2004-08-26

申请号：US10770426

申请日：2004-02-04

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Toshihiro Nishii

IPC分类号： H05K001/00 ,  H05K003/10

CPC分类号： H05K3/0032 ,  H05K1/116 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09909 ,  H05K2203/0191 ,  H05K2203/0537 ,  H05K2203/065 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T428/24917 ,  Y10T428/249953

摘要： In order to improve the adhesion of a circuit to a circuit forming board, a separation film (4) comprising a base film and a coating layer formed on the base film is joined to both the sides of the board (1). When a laser beam (5) is applied to form a throughhole (6) in the board (1), a unified portion (7) of the board (1) and the separation film (4) is formed around the throughhole (6). An energy beam is applied to the whole or a part of the surface of a circuit formed at a circuit forming step to transfer a part of the separation file. Thus, a high density board where the circuit strongly adheres to the board can be realized in the manufacturing process of the circuit forming board.

摘要翻译： 为了提高电路与电路形成基板的密合性，在基板（1）的两面接合包含基膜和形成在基膜上的被覆层的分离膜（4）。 当在板（1）中施加激光束（5）以形成通孔（6）时，围绕通孔（6）形成板（1）和分离膜（4）的统一部分（7） 。 能量束被施加到形成在电路形成步骤的电路的整个表面或一部分表面以传送分离文件的一部分。 因此，在电路形成板的制造工艺中可以实现电路强烈粘附于电路板的高密度板。

公开(公告)号：US20040078969A1

公开(公告)日：2004-04-29

申请号：US10634089

申请日：2003-08-04

发明人： Hideo Kanzawa ,  Satoru Yuuhaku ,  Yoshitake Hayashi

IPC分类号： H05K003/10 ,  H01K003/22

CPC分类号： H05K3/205 ,  H01L21/4867 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2225/1035 ,  H05K1/185 ,  H05K1/187 ,  H05K3/207 ,  H05K2203/0568 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

摘要： A method of manufacturing a circuit board by forming a circuit pattern in a short process and capable of performing pattern transfer with stability. The manufacturing method includes a step of superposing on a carrier a resist layer in which a circuit pattern is formed and which is formed of a conductor or an insulator, a step of filling the circuit pattern with an electroconductive material, a step of removing the resist layer from the carrier, and a step of transferring the electroconductive material filled in the circuit pattern into an electrical insulating material.

摘要翻译： 一种通过在短时间内形成电路图案并且能够稳定地执行图案转印来制造电路板的方法。 该制造方法包括在载体上叠加其中形成电路图案并由导体或绝缘体形成的抗蚀剂层的步骤，用导电材料填充电路图案的步骤，除去抗蚀剂的步骤 层，以及将填充在电路图案中的导电材料转印到电绝缘材料中的步骤。

公开(公告)号：US20040020046A1

公开(公告)日：2004-02-05

申请号：US10433938

申请日：2003-06-06

发明人： Takeshi Suzuki ,  Satoru Tomekawa ,  Yosihiro Tomita ,  Yuichiro Sugita ,  Shigeru Yamane

IPC分类号： H05K003/10 ,  H01M002/16

CPC分类号： B82Y25/00 ,  B22F9/007 ,  B22F9/008 ,  B22F2999/00 ,  C22C1/0441 ,  C22C38/002 ,  C22C38/005 ,  C22C38/12 ,  C22C38/14 ,  H01B1/22 ,  H01F1/0574 ,  H01F1/0579 ,  H01F1/058 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/29 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/0106 ,  H01L2924/01065 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/12042 ,  H01L2924/30105 ,  H05K1/095 ,  H05K3/4069 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2203/1461 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/13099 ,  H01L2924/3512 ,  H01L2924/00 ,  B22F1/0044 ,  B22F9/08

摘要： The present invention provides a method for manufacturing a conductive paste. The method includes deforming conductive particles so that a deformation degree is 1.01 to 1.5 by application of a stress to the conductive particles and mixing the deformed conductive particles with a binder that includes a thermosetting resin as the main component. The deformation degree is determined by dividing an average diameter of the conductive particles after deformation by an average diameter of the conductive particles before deformation, where the average diameter is measured by a laser diffraction method. The use of this conductive paste for a prepreg sheet having limited compressibility can suppress a short circuit between via holes and the degradation of insulation properties.

摘要翻译： 本发明提供一种导电糊的制造方法。 该方法包括通过对导电颗粒施加应力并使变形的导电颗粒与包含热固性树脂作为主要成分的粘合剂混合而使导电颗粒变形，使得变形度为1.01至1.5。 通过将变形后的导电粒子的平均直径除以变形前的导电粒子的平均直径，通过激光衍射法测定平均直径，求出变形度。 通过使用这种导电性糊料来抑制压缩性有限的预浸料片，可以抑制通孔之间的短路和绝缘性能的劣化。

公开(公告)号：US20040012942A1

公开(公告)日：2004-01-22

申请号：US10618511

申请日：2003-07-11

申请人： INFICON GmbH

发明人： Per Bjoerkman ,  Ray Olsson

IPC分类号： H01G007/00 ,  H05K007/04 ,  H05K003/10

CPC分类号： G01L9/0075 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49007 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/49224

摘要： A capacitive vacuum measuring cell includes first and second ceramic housing bodies (1, 4) joined by an edge seal (3). A thin ceramic membrane (2) is supported between first and second housing bodies (1, 4) by the edge seal (3) at a small distance from the first housing body (1) creating a reference vacuum chamber (25) therebetween. An electrically conductive material (7) coats opposing surfaces of the first housing body (1) and the membrane (2) to form a capacitor. A measurement vacuum chamber (26) is provided between the membrane (2) and the second housing body (4). A port (5) communicates with the second housing body (4) to connect the measurement vacuum chamber (26) of the measuring cell to the medium to be measured. The membrane (2) is made from an Al2O3 slurry that is sintered in a first heating step, cooled, and then reheated to smooth the membrane.

摘要翻译： 电容式真空测量单元包括通过边缘密封件（3）连接的第一和第二陶瓷壳体（1,4）。 薄壁陶瓷膜（2）通过边缘密封（3）在与第一壳体（1）相距很小的距离处被支撑在第一和第二壳体（1,4）之间，从而在它们之间形成参考真空室（25）。 导电材料（7）涂覆第一壳体（1）和膜（2）的相对表面以形成电容器。 在膜（2）和第二壳体（4）之间设置测量真空室（26）。 端口（5）与第二壳体（4）连通，将测量室的测量真空室（26）连接到待测介质。 膜（2）由在第一加热步骤中烧结的Al 2 O 3浆料制成，冷却，然后再加热以使膜平滑。