公开(公告)号：US08253030B2

公开(公告)日：2012-08-28

申请号：US12948894

申请日：2010-11-18

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/11

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A printed wiring board includes a main body having a mounting portion and ground and power supply pads in the mounting portion such that a ground line of a semiconductor device is connected to a ground pad and a power supply line of the device is connected to a power supply pad, and a layered capacitor disposed in the main body and having a high dielectric constant layer and first and second layer electrodes sandwiching the dielectric layer. One of the electrodes is connected to the power supply line and the other electrode is connected to the ground line, the first electrode has a solid pattern including passage holes through which second rod terminals connected to the second electrode pass in a non-contacting manner, and the second electrode has a solid pattern including passage holes through which first rod terminals connected to the first electrode pass in a non-contacting manner.

Abstract translation: 一种印刷电路板，包括具有安装部分的主体和安装部分中的接地和电源焊盘，使得半导体器件的接地线连接到接地焊盘，并且该设备的电源线连接到电源 供电焊盘和设置在主体中并具有高介电常数层的层状电容器和夹着介电层的第一和第二层电极。 电极中的一个连接到电源线，另一个电极连接到接地线，第一电极具有固体图案，其包括通孔，第二电极与第二电极连接，第二电极以非接触的方式通过， 并且第二电极具有固体图案，其包括通孔，通过该通孔与第一电极连接的第一杆端子以非接触方式通过。

公开(公告)号：US08164920B2

公开(公告)日：2012-04-24

申请号：US11917418

申请日：2006-06-13

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/11 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract translation: 一种印刷线路板包括：安装部，在该安装部上可以搭载有单个芯片的两个处理器芯的双芯处理器，电源线，接地线以及第一分层电容器和第二分层电容器， 处理器核心。 因此，即使当处理器核心的电位瞬时下降时，也可以通过分别对应于处理器核心的分层电容器的作用来抑制电位的瞬时下降。 此外，即使处理器核心中的一个的电压变化，电压的变化也不影响其他的处理器核心，因此不会发生故障。

公开(公告)号：US08124882B2

公开(公告)日：2012-02-28

申请号：US12419007

申请日：2009-04-06

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US08119040B2

公开(公告)日：2012-02-21

申请号：US12286207

申请日：2008-09-29

Applicant: Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

Inventor： Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

IPC: H01B1/02

CPC classification number: H05K1/162 ,  H01L2924/0103 ,  H01L2924/01057 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/167 ,  H05K2201/09763

Abstract: A method for forming an embedded passive device module comprises depositing a first amount of an alkali silicate material, co-depositing an amount of embedded passive device material with the amount of alkali silicate material; and thermally processing the amount of alkali silicate material and the amount of embedded passive device material at a temperature sufficient to cure the amount of alkali silicate material and the amount of embedded passive device material and form a substantially moisture free substrate.

Abstract translation: 一种用于形成嵌入式无源器件模块的方法，包括沉积第一量的碱金属硅酸盐材料，将一定量的嵌入的无源器件材料与一定量的碱金属硅酸盐材料共沉积; 并且在足以固化碱金属硅酸盐材料的量和嵌入的无源器件材料的量并形成基本上无水的衬底的温度下热处理碱金属硅酸盐材料的量和嵌入的无源器件材料的量。

公开(公告)号：US08064215B2

公开(公告)日：2011-11-22

申请号：US12230872

申请日：2008-09-05

Applicant: Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

Inventor： Yul-Kyo Chung ,  Sung Yi ,  Soon-Gyu Yim ,  Seog-Moon Choi ,  Jin-Gu Kim ,  Young-Do Kweon

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/25 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.

Abstract translation: 公开了一种半导体芯片封装和具有嵌入式半导体芯片封装的印刷电路板。 半导体芯片封装可以包括在一侧形成有至少一个芯片焊盘的半导体芯片和形成在半导体芯片的另一侧上的电容器。

公开(公告)号：US20110252638A1

公开(公告)日：2011-10-20

申请号：US13170348

申请日：2011-06-28

Applicant: Hironori TANAKA

Inventor： Hironori TANAKA

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including an insulation layer and a first interlayer resin insulation layer provided on the insulation layer. A layered capacitor section is provided on the first interlayer resin insulation layer and has a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. Also included is a second interlayer resin insulation layer provided on the first interlayer resin insulation layer and the layered capacitor section, and a metal thin-film layer provided over the layered capacitor section and on the second interlayer resin insulation layer. An outermost interlayer resin insulation layer is provided on the second interlayer resin insulation layer and the metal thin-film layer, and a mounting section is provided on the outermost interlayer resin insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each interlayer resin insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals, and second via conductors that electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在所述绝缘层上的绝缘层和第一层间树脂绝缘层。 层叠电容器部分设置在第一层间树脂绝缘层上，并且具有高电介质层和夹在高电介质层中的第一和第二层状电极。 还包括设置在第一层间树脂绝缘层和层状电容器部分上的第二层间树脂绝缘层和设置在层状电容器部分和第二层间树脂绝缘层上的金属薄膜层。 在第二层间树脂绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层，并且在最外层的层间树脂绝缘层上设置安装部，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个层间树脂绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体和将第二层状电极电连接到第二外部端子的第二通路导体。

公开(公告)号：US07989916B2

公开(公告)日：2011-08-02

申请号：US12590547

申请日：2009-11-10

Applicant: John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

Inventor： John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

IPC: H01L21/02

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract translation: 一种物品包括埋在焊接掩模中的顶部电极。 一种物品包括在核心结构上的顶部电极。 形成顶部电极的工艺包括减小焊接掩模厚度并在厚度较薄的焊接掩模上形成顶部电极。 形成顶部电极的工艺包括在位于芯结构的图案化部分中的高K电介质上形成顶部电极。

公开(公告)号：US07936568B2

公开(公告)日：2011-05-03

申请号：US11882645

申请日：2007-08-03

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/162 ,  H05K3/007 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/435

Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capacitors and one end side of the through electrode.

Abstract translation: 本发明的电容器内置基板包括： 基础树脂层; 在电容器通过基底树脂层的状态下，沿横向方向并排布置的多个电容器，每个电容器由设置成穿过基础树脂层并具有从两个突出部分突出的突出部分的第一电极构成 基底树脂层的表面侧分别使得基底树脂层的一个表面侧上的突出部分用作连接部分，用于覆盖基础树脂层的另一表面侧上的第一电极的突出部分的电介质层， 和用于覆盖电介质层的第二电极; 通孔，其设置成穿过所述基底树脂层，并且具有分别从所述基底树脂层的两个表面侧突出的突出部分; 以及形成在基础树脂层的另一面侧并与电容器的第二电极和贯通电极的一端侧连接的积层布线。

公开(公告)号：US20110018099A1

公开(公告)日：2011-01-27

申请号：US12933522

申请日：2009-03-24

Applicant: Masaki Muramatsu

Inventor： Masaki Muramatsu

IPC: H01L27/08

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/02 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 10 includes a core substrate 11, a first capacitor 301, a wiring laminate portion 31, and a second capacitor 101. An accommodation hole portion 90 of the core substrate 11 accommodates the first capacitor 101 therein, and a component-mounting region 20 is set on a surface 39 of the wiring laminate portion 31. The second capacitor 101 has electrode layers 102, 103 and a dielectric layer 104. The second capacitor 101 is embedded in the wiring laminate portion 31 in such a state that first main surfaces 105, 107 and second main surfaces 106, 108 are in parallel with the surface 39 of the wiring laminate portion 31, and is disposed between the first capacitor 301 and the component-mounting region 20.

Abstract translation: 目的是提供一种能够解决由连接部件和电容器的布线的长度增加引起的问题的配有部件的布线基板。 构成部件的布线基板10具有芯基板11，第一电容器301，布线层叠部31和第二电容器101.芯基板11的容纳孔部90容纳第一电容器101， 安装区域20设置在布线层叠部分31的表面39上。第二电容器101具有电极层102,103和电介质层104.第二电容器101以这样的状态嵌入布线层叠部分31中 第一主表面105,107和第二主表面106,108与布线层压体部分31的表面39平行，并且设置在第一电容器301和部件安装区域20之间。

公开(公告)号：US20100270645A1

公开(公告)日：2010-10-28

申请号：US12763433

申请日：2010-04-20

Applicant: DAVID ROSS MCGREGOR ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

Inventor： DAVID ROSS MCGREGOR ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

IPC: H01L29/86 ,  H01L21/768 ,  H01L21/50 ,  H01L23/522

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/1126

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

Abstract translation: 提供了包括通过堆积层附着到印刷线路板芯的至少一个薄膜电容器的半导体封装，其中薄膜电容器的第一电极包括薄镍箔，薄膜电容器的第二电极 包括铜电极，并且在镍箔上形成铜层。 薄膜电容器和半导体器件之间的互连提供了将电荷转移到半导体器件和从半导体器件传输电荷的低电感路径。 还提供了制造这种半导体封装的方法。