公开(公告)号：US09470987B1

公开(公告)日：2016-10-18

申请号：US14920859

申请日：2015-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Yi-Jing Wang ,  Chia-Hsun Tseng

IPC: G03F7/00 ,  H01L21/30 ,  H01L21/02 ,  H01L21/32 ,  H01L21/26 ,  H01L21/31 ,  G03F7/20 ,  H01L21/266 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/027

CPC classification number: G03F7/70633 ,  H01L21/02642 ,  H01L21/027 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139

Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.

Abstract translation: 覆盖掩模包括多个第一图案，多个第二图案和多个第三图案。 第一图案布置在第一间距之内。 第二图案布置在第二间距内。 第三图案的第一部分在第一间距内与第一图案交替布置，并且第三图案的第二部分在第二间距内与第二图案交替布置，并且第一间距不等于 第二音调

公开(公告)号：US20160300923A1

公开(公告)日：2016-10-13

申请号：US15188998

申请日：2016-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/165 ,  H01L29/24 ,  H01L29/78 ,  H01L29/161

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A semiconductor device includes: a substrate, a fin-shaped structure on the substrate, and a dummy fin-shaped structure on the substrate and adjacent to the fin-shaped structure. Preferably, the fin-shaped structure includes a gate structure thereon and a first epitaxial layer adjacent to two sides of the gate structure, and the dummy fin-shaped structure includes a second epitaxial layer thereon. A contact plug is disposed on the first epitaxial layer and the second epitaxial layer. In addition, the dummy fin-shaped structure includes a curve, in which the curve is omega shaped.

Abstract translation: 半导体器件包括：衬底，在衬底上的鳍状结构，以及在衬底上并与鳍状结构相邻的虚拟鳍状结构。 优选地，鳍状结构包括其上的栅极结构和与栅极结构的两侧相邻的第一外延层，并且虚拟鳍状结构在其上包括第二外延层。 接触插塞设置在第一外延层和第二外延层上。 此外，虚拟鳍状结构包括曲线，其中曲线是Ω形的。

公开(公告)号：US20160299433A1

公开(公告)日：2016-10-13

申请号：US14714357

申请日：2015-05-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: G03F7/20 ,  G03F7/36

CPC classification number: G03F7/203 ,  G03F7/2002 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/7025

Abstract: An illumination system includes a light source used to generate a light and an opaque plate. The opaque plate is disposed between the light source and a photomask and includes an annular aperture and an aperture dipole. The annular aperture has an inner side and an outer side. The aperture dipole includes at least one first aperture and at least one second aperture. The first aperture and the second aperture connected to the annular aperture respectively and protruding out from the outer side of the annular aperture are disposed symmetrically with respect to a center of the annular aperture.

Abstract translation: 照明系统包括用于产生光和不透明板的光源。 不透明板设置在光源和光掩模之间，并且包括环形孔和孔偶极子。 环形孔具有内侧和外侧。 孔径偶极子包括至少一个第一孔径和至少一个第二孔径。 分别连接到环形孔并从环形孔的外侧突出的第一孔和第二孔相对于环形孔的中心对称设置。

公开(公告)号：US20160204197A1

公开(公告)日：2016-07-14

申请号：US14612300

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09385220B2

公开(公告)日：2016-07-05

申请号：US14588989

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A semiconductor device includes: a substrate, a fin-shaped structure on the substrate, and a dummy fin-shaped structure on the substrate and adjacent to the fin-shaped structure. Preferably, the fin-shaped structure includes a gate structure thereon and a first epitaxial layer adjacent to two sides of the gate structure, and the dummy fin-shaped structure includes a second epitaxial layer thereon. A contact plug is disposed on the first epitaxial layer and the second epitaxial layer.

Abstract translation: 半导体器件包括：衬底，在衬底上的鳍状结构，以及在衬底上并与鳍状结构相邻的虚拟鳍状结构。 优选地，鳍状结构包括其上的栅极结构和与栅极结构的两侧相邻的第一外延层，并且虚拟鳍状结构在其上包括第二外延层。 接触插塞设置在第一外延层和第二外延层上。

公开(公告)号：US09373505B2

公开(公告)日：2016-06-21

申请号：US14278296

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Ying Huang ,  Jen-Hsiu Li ,  Mei-Chen Chen ,  Ya-Ling Chen ,  Yi-Jing Wang ,  Chi-Ming Huang

IPC: H01L23/544 ,  H01L21/033

CPC classification number: H01L21/0334 ,  H01L21/0337 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In this disclosure, a mark segmentation method and a method for manufacturing a semiconductor structure applying the same are provided. The mark segmentation method comprises the following steps. First, a plurality of segments having a width WS and separated from each other by a space SS formed on a substrate are identified by a processor. Thereafter, a plurality of marks are set over the segments by the processor. This step comprises: (1) adjusting a width WM of each one of the marks being equal to m(WS+SS)+WS or m(WS+SS)+SS by the processor, wherein m is an integer; and (2) adjusting a space SM of adjacent two of the marks by the processor such that WM+SM=n(WS+SS), wherein n is an integer.

Abstract translation: 在本公开中，提供了一种标记分割方法及其制造应用该半导体结构的方法。 标记分割方法包括以下步骤。 首先，通过处理器识别具有宽度WS并且由形成在基板上的空间SS彼此分离的多个段。 此后，处理器在片段上设置多个标记。 该步骤包括：（1）处理器调整每一个标记的宽度WM等于m（WS + SS）+ WS或m（WS + SS）+ SS，其中m是整数; 和（2）由处理器调整相邻两个标记的空格SM，使得WM + SM = n（WS + SS），其中n是整数。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160103396A1

公开(公告)日：2016-04-14

申请号：US14512484

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70466 ,  G03F7/70625

Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.

Abstract translation: 双重图案化方法包括以下步骤。 首先，提供堆叠在其上的目标层和掩模层。 接下来，在掩模层中形成第一图案开口，并且测量第一图案开口的宽度以获得测量值。 然后，基于测量值在掩模层中形成第二图案开口，其中第二图案开口和第一图案开口是共面的。 最后，执行偏置修剪处理以修剪第一图案开口和第二图案开口。

公开(公告)号：US09304389B2

公开(公告)日：2016-04-05

申请号：US14067986

申请日：2013-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Sho-Shen Lee ,  Wen-Liang Huang ,  Chang-Mao Wang ,  Kai-Lin Chuang

IPC: G03F1/68 ,  G03F1/00

CPC classification number: G03F1/00 ,  G03F1/50 ,  G03F1/68

Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.

Abstract translation: 提供包括第一不透明图案和第二不透明图案的光掩模。 第一不透明图案分布在光掩模中限定的第一平面中，而第二不透明图案设置在第一不透明图案之上并与第一不透明图案隔开。 换句话说，第一不透明图案和第二不透明图案不分布在同一平面中。

公开(公告)号：US20160093536A1

公开(公告)日：2016-03-31

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。