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    Conditional cell placement
    21.
    发明授权
    Conditional cell placement 有权
    条件细胞放置

    公开(公告)号：US08560997B1

    公开(公告)日：2013-10-15

    申请号：US13557578

    申请日：2012-07-25

    Applicant: Ping-Lin Yang ,  Ming-Zhang Kuo ,  Cheng-Chung Lin ,  Jimmy Hsiao ,  Jia-Rong Hsu

    Inventor： Ping-Lin Yang ,  Ming-Zhang Kuo ,  Cheng-Chung Lin ,  Jimmy Hsiao ,  Jia-Rong Hsu

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.

    Abstract translation: 其中还提供了一种或多种用于条件单元放置的技术。 在一个实施例中，为第一小区创建条件边界。 例如，条件边界使得能够基于条件放置规则相对于第二单元放置第一单元。 在一个实施例中，基于第一情况，第一小区相对于第二小区以第一方式放置。 在第二种情况下，与第一种情况不同，第一单元相对于第二单元以第二种方式放置。 以这种方式，提供条件单元布置，从而提供例如关于半导体制造的灵活性和改进的布局效率。

    POWER SUPPLY CIRCUIT FOR PCI-E SLOT
    23.
    发明申请
    POWER SUPPLY CIRCUIT FOR PCI-E SLOT 有权
    PCI-E SLOT电源电路

    公开(公告)号：US20120161849A1

    公开(公告)日：2012-06-28

    申请号：US13048973

    申请日：2011-03-16

    Applicant: CHENG-CHUNG LIN ,  WU JIANG

    Inventor： CHENG-CHUNG LIN ,  WU JIANG

    IPC: H03K17/687

    CPC classification number: G06F1/26

    Abstract: A power supply circuit for a PCI-E slot includes a control chip, a first electronic switch, and a second electronic switch. The control chip determines a status of a motherboard, outputting a control signal. A first terminal of the first electronic switch is connected to the control chip to receive the control signal, and connected to a +3.3V dual power supply of the motherboard through a first resistor. A second terminal of the first electronic switch is grounded. A third terminal of the first electronic switch is connected to a first terminal of the second electronic switch, and connected to the +3.3V dual power supply through a second resistor. A second terminal of the second electronic switch is connected to the +3.3V dual power supply. A third terminal of the second electronic switch is connected to a PCI-E slot.

    Abstract translation: 用于PCI-E插槽的电源电路包括控制芯片，第一电子开关和第二电子开关。 控制芯片确定主板的状态，输出控制信号。 第一电子开关的第一端子连接到控制芯片以接收控制信号，并通过第一电阻器连接到主板的+ 3.3V双电源。 第一个电子开关的第二个端子接地。 第一电子开关的第三端子连接到第二电子开关的第一端子，并通过第二电阻器连接到+ 3.3V双电源。 第二个电子开关的第二个端子连接到+ 3.3V双电源。 第二电子开关的第三端子连接到PCI-E插槽。

    Surface treatment of metal interconnect lines
    25.
    发明申请
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US20060001160A1

    公开(公告)日：2006-01-05

    申请号：US11213238

    申请日：2005-08-26

    Applicant: Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    Inventor： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  B32B15/00 ,  B32B17/06

    CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    Abstract translation: 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

    Surface treatment of metal interconnect lines
    26.
    发明授权
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US06955984B2

    公开(公告)日：2005-10-18

    申请号：US10439358

    申请日：2003-05-16

    Applicant: Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Dai Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    Inventor： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Dai Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC: H01L21/288 ,  H01L21/44 ,  H01L21/445 ,  H01L21/768

    CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    Abstract translation: 用于形成半导体结构的方法和装置包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

    Method to improve stability and reliability of CVD low K dielectric
    28.
    发明授权
    Method to improve stability and reliability of CVD low K dielectric 失效
    提高CVD低K电介质稳定性和可靠性的方法

    公开(公告)号：US06794295B1

    公开(公告)日：2004-09-21

    申请号：US09579542

    申请日：2000-05-26

    Applicant: Cheng Chung Lin ,  Lain-Jong Li

    Inventor： Cheng Chung Lin ,  Lain-Jong Li

    IPC: H01L21302

    CPC classification number: H01L21/02211 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76807

    Abstract: A process for depositing, through plasma enhanced chemical vapor deposition, inorganic films having low dielectric constant is disclosed. After deposition under low power for a few seconds the power is raised to high for a few seconds, deposition of the film continuing to alternate between low and high power modes until the total desired thickness is reached. Additionally, for the deposition of materials such as black diamond, oxygen is added to the plasma during the high power phase (and removed during the low power phase). We have found that films deposited in this way have low flat band voltages, close to zero, and are, in general, more robust than films deposited according to prior art methods. In particular, these films are free of the cracking problems often encountered during chemical mechanical polishing of films of this type during the formation of damascene structures.

    Abstract translation: 公开了通过等离子体增强化学气相沉积沉积具有低介电常数的无机膜的方法。 在低功率下沉积几秒钟之后，功率升高到几秒钟，膜的沉积继续在低功率模式和高功率模式之间交替，直到达到总的期望厚度。 另外，对于诸如黑色金刚石的材料的沉积，在高功率阶段期间将氧气加入到等离子体中（并且在低功率阶段期间被除去）。 我们已经发现以这种方式沉积的薄膜具有接近于零的低平带电压，并且通常比根据现有技术方法沉积的薄膜更坚固。 特别地，这些膜在形成镶嵌结构期间没有这种类型的膜的化学机械抛光期间经常遇到的龟裂问题。

    Method of reducing dishing and erosion using a sacrificial layer
    30.
    发明授权
    Method of reducing dishing and erosion using a sacrificial layer 有权
    使用牺牲层减少凹陷和侵蚀的方法

    公开(公告)号：US06383935B1

    公开(公告)日：2002-05-07

    申请号：US09687162

    申请日：2000-10-16

    Applicant: Cheng Chung Lin ,  Chen Hua Yu ,  Tsu Shih ,  Weng Chang

    Inventor： Cheng Chung Lin ,  Chen Hua Yu ,  Tsu Shih ,  Weng Chang

    IPC: H01L214763

    CPC classification number: H01L21/7684

    Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

    Abstract translation: 已知化学机械抛光（CMP）在平坦化表面包括部分填充有金属的宽沟槽时引起凹陷。 首先用在CMP下的抛光速率与沟槽中的金属相似的材料填充沟槽已经克服了这个问题。 旋转涂层用于此，使得只有沟槽被填充。 在CMP之后，除去该材料的任何残余物，留下已经被平坦化到预期程度的表面，而不引入显着的凹陷并且金属的最小侵蚀。

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