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    LATERAL BIPOLAR TRANSISTOR AND METHOD OF PRODUCTION
    21.
    发明申请
    LATERAL BIPOLAR TRANSISTOR AND METHOD OF PRODUCTION 有权
    侧向双极晶体管和生产方法

    公开(公告)号：US20080290463A1

    公开(公告)日：2008-11-27

    申请号：US11752734

    申请日：2007-05-23

    Applicant: Matthias Stecher

    Inventor： Matthias Stecher

    IPC: H01L21/331 ,  H01L27/082

    CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821

    Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

    Abstract translation: 双极晶体管的发射极和集电极区域由相同导电类型的掺杂区域形成，这些掺杂区域由相反导电类型的掺杂半导体材料分开，分立的掺杂区域被布置在半导体主体的表面，并且位于 与在半导体本体的表面处被引入到沟槽中的导电材料电接触。

    Semiconductor component with passivation layer
    24.
    发明申请
    Semiconductor component with passivation layer 有权
    半导体元件具有钝化层

    公开(公告)号：US20060163742A1

    公开(公告)日：2006-07-27

    申请号：US11313178

    申请日：2005-12-20

    Applicant: Matthias Stecher

    Inventor： Matthias Stecher

    IPC: H01L23/48

    CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/958 ,  H01L2924/00

    Abstract: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.

    Abstract translation: 半导体部件具有半导体本体，并且还具有设置在半导体主体上方的金属/绝缘结构，并且具有彼此横向相邻的多个金属区域和绝缘区域。 金属区域用于向半导体体提供电流。 此外，半导体部件具有布置在金属/绝缘结构上的钝化层。 钝化层包括金属或含金属的化合物。

    Vertical bipolar transistor
    25.
    发明授权
    Vertical bipolar transistor 有权
    垂直双极晶体管

    公开(公告)号：US06894367B2

    公开(公告)日：2005-05-17

    申请号：US10367005

    申请日：2003-02-14

    Applicant: Peter Nelle ,  Matthias Stecher

    Inventor： Peter Nelle ,  Matthias Stecher

    IPC: H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732 ,  H01L29/739 ,  H01L27/082

    CPC classification number: H01L29/7322 ,  H01L27/0744 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/739

    Abstract: A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET. This results in a considerable increase in the collector-emitter breakdown voltage up to 30 V or more being possible without having to except limitations with regard to dielectric strength and on resistivity

    Abstract translation: 垂直双极晶体管具有并入外延层中的J-FET。 J-FET的夹断电压小于没有J-FET的双极晶体管的集电极 - 发射极击穿电压。 这导致集电极 - 发射极击穿电压的高达30V或更高的可能性，而不必除了关于介电强度和电阻率的限制之外

    Method for producing bridged doped zones
    26.
    发明授权
    Method for producing bridged doped zones 有权
    生产桥接掺杂区的方法

    公开(公告)号：US6146976A

    公开(公告)日：2000-11-14

    申请号：US461444

    申请日：1999-12-14

    Applicant: Matthias Stecher ,  Tim Gutheit ,  Werner Schwetlick

    Inventor： Matthias Stecher ,  Tim Gutheit ,  Werner Schwetlick

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L21/76

    CPC classification number: H01L29/0696 ,  H01L29/0649 ,  H01L29/7809

    Abstract: Bridged, doped zones are formed in a semiconductor. A silicon nitride layer is deposited and structured on a semi-conductor region with a predetermined dopant concentration. The structure is subjected to thermal oxidation, with the result that at least one oxide region and at least two oxide-free regions, which are separated from one another by the oxide region, are produced on the surface of the semiconductor region. A dopant is introduced into the oxide-free regions and driven into the semiconductor region. A coherent zone is thus produced in the semiconductor region with a dopant concentration at least ten times the dopant concentration of the semiconductor region. This produces a coherent zone having a high dopant concentration which is bridged by the oxide region which separates the oxide-free regions on the surface of the semiconductor region. Conductive layers, such as a polysilicon layer or a metal layer, for example, can be formed on the oxide region (oxide bridge), with the assurance the conductive layer is completely insulated from the doped zone.

    Abstract translation: 桥接，掺杂区形成在半导体中。 在具有预定掺杂剂浓度的半导体区域上沉积和构造氮化硅层。 对该结构进行热氧化，结果是在半导体区域的表面上产生至少一个氧化物区域和由氧化物区域彼此分开的至少两个无氧化物区域。 将掺杂剂引入到无氧化物区域并被驱入半导体区域。 因此，在半导体区域中产生相干区域，其掺杂剂浓度至少为半导体区域的掺杂剂浓度的十倍。 这产生具有高掺杂剂浓度的相干区域，其由分离半导体区域的表面上的无氧化物区域的氧化物区域桥接。 可以在氧化物区域（氧化物桥）上形成诸如多晶硅层或金属层的导电层，同时保证导电层与掺杂区完全绝缘。

    Method of producing a transistor structure
    27.
    发明授权
    Method of producing a transistor structure 失效
    晶体管结构的制造方法

    公开(公告)号：US6057201A

    公开(公告)日：2000-05-02

    申请号：US25211

    申请日：1998-02-18

    Applicant: Matthias Stecher

    Inventor： Matthias Stecher

    IPC: H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L21/28

    CPC classification number: H01L29/66659 ,  H01L29/1087 ,  H01L29/7833

    Abstract: The method produces transistor structures with a smaller contact opening, without having to take multiple adjustment allowances into account. Moreover, the method provides two zones of a second conductivity type, which have different dopant concentrations, so that a more gentle transition in the drain doping is obtained. The gentler transition in drain doping effects a lowering in the peak field intensity that can release hot electrons. Thus a degradation of the first insulating layer (gate oxide) caused by hot electrons is prevented.

    Abstract translation: 该方法产生具有较小接触开口的晶体管结构，而不必考虑多个调整余量。 此外，该方法提供具有不同掺杂剂浓度的第二导电类型的两个区域，使得获得在漏极掺杂中更平缓的转变。 漏极掺杂中的温和过渡导致能够释放热电子的峰值场强的降低。 因此，防止由热电子引起的第一绝缘层（栅极氧化物）的劣化。

    Integrated circuit and production method
    28.
    发明授权
    Integrated circuit and production method 有权
    集成电路及生产方法

    公开(公告)号：US08569865B2

    公开(公告)日：2013-10-29

    申请号：US13424792

    申请日：2012-03-20

    Applicant: Matthias Stecher

    Inventor： Matthias Stecher

    IPC: H01L21/70

    CPC classification number: H01L21/761 ,  H01L21/823878 ,  H01L27/0629 ,  H01L29/7809 ,  H01L29/7811

    Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

    Abstract translation: 公开了集成电路和制造方法。 一个实施例在半导体阱中形成反向电流复合物，使得形成有害的反向电流的电荷载流子不能流入衬底。

    Vertical Transistor with Improved Robustness
    29.
    发明申请
    Vertical Transistor with Improved Robustness 有权
    具有提高鲁棒性的垂直晶体管

    公开(公告)号：US20130026561A1

    公开(公告)日：2013-01-31

    申请号：US13194362

    申请日：2011-07-29

    Applicant: Rainald Sander ,  Markus Winkler ,  Michael Asam ,  Matthias Stecher

    Inventor： Rainald Sander ,  Markus Winkler ,  Michael Asam ,  Matthias Stecher

    IPC: H01L29/78

    CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7805

    Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.

    Abstract translation: 公开了一种包括具有第一水平表面的半导体本体的晶体管。 漂移区布置在半导体本体中。 多个栅极布置在半导体本体的沟槽中。 沟槽具有纵向并相对于彼此平行延伸。 沟槽的纵向方向在半导体本体的第一横向延伸。 主体区域和源区域布置在沟槽之间。 主体区域在半导体本体的垂直方向上布置在漂移区域和源极区域之间。 在第一水平表面中，源区域和主体区域在第一横向上交替布置。 源电极电连接到第一水平表面中的源极区域和主体区域。

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