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    MANAGING VARIATIONS AMONG NODES IN PARALLEL SYSTEM FRAMEWORKS
    21.
    发明申请
    MANAGING VARIATIONS AMONG NODES IN PARALLEL SYSTEM FRAMEWORKS 审中-公开

    公开(公告)号：US20170279703A1

    公开(公告)日：2017-09-28

    申请号：US15081558

    申请日：2016-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Samuel Lawrence Wasmundt ,  Leonardo Piga ,  Indrani Paul ,  Wei Huang ,  Manish Arora

    IPC: H04L12/26 ,  H04L29/08

    CPC classification number: H04L43/16 ,  H04L43/08 ,  H04L67/10 ,  H04L67/1008

    Abstract: Systems, apparatuses, and methods for managing variations among nodes in parallel system frameworks. Sensor and performance data associated with the nodes of a multi-node cluster may be monitored to detect variations among the nodes. A variability metric may be calculated for each node of the cluster based on the sensor and performance data associated with the node. The variability metrics may then be used by a mapper to efficiently map tasks of a parallel application to the nodes of the cluster. In one embodiment, the mapper may assign the critical tasks of the parallel application to the nodes with the lowest variability metrics. In another embodiment, the hardware of the nodes may be reconfigured so as to reduce the node-to-node variability.

    POWER MANAGEMENT FOR HETEROGENEOUS COMPUTING SYSTEMS
    25.
    发明申请
    POWER MANAGEMENT FOR HETEROGENEOUS COMPUTING SYSTEMS 审中-公开

    公开(公告)号：US20170083077A1

    公开(公告)日：2017-03-23

    申请号：US14857574

    申请日：2015-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/329 ,  Y02D10/171 ,  Y02D10/24

    Abstract: A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

    INDEPENDENT BETWEEN-MODULE PREFETCHING FOR PROCESSOR MEMORY MODULES
    26.
    发明申请
    INDEPENDENT BETWEEN-MODULE PREFETCHING FOR PROCESSOR MEMORY MODULES 审中-公开
    处理器存储器模块的独立模块预编译

    公开(公告)号：US20160378667A1

    公开(公告)日：2016-12-29

    申请号：US14747933

    申请日：2015-06-23

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David Andrew Roberts ,  Mitesh R. Meswani ,  Sergey Blagodurov ,  Dmitri Yudanov ,  Indrani Paul

    IPC: G06F12/08

    CPC classification number: G06F12/0862 ,  G06F2212/6024

    Abstract: A processor employs multiple prefetchers at a processor to identify patterns in memory accesses to different memory modules. The memory accesses can include transfers between the memory modules, and the prefetchers can prefetch data directly from one memory module to another based on patterns in the transfers. This allows the processor to efficiently organize data at the memory modules without direct intervention by software or by a processor core, thereby improving processing efficiency.

    Abstract translation: 处理器在处理器中使用多个预取器来识别对不同存储器模块的存储器访问中的模式。 存储器访问可以包括存储器模块之间的传输，并且预取器可以基于传输中的模式将数据直接从一个存储器模块预取到另一个。 这允许处理器在存储器模块内有效地组织数据，而无需软件或处理器核心的直接干预，从而提高处理效率。

    CONTROL OF THERMAL ENERGY TRANSFER FOR PHASE CHANGE MATERIAL IN DATA CENTER
    27.
    发明申请
    CONTROL OF THERMAL ENERGY TRANSFER FOR PHASE CHANGE MATERIAL IN DATA CENTER 审中-公开
    数据中心相变材料热能转移控制

    公开(公告)号：US20160338230A1

    公开(公告)日：2016-11-17

    申请号：US14709655

    申请日：2015-05-12

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Fulya Kaplan ,  Manish Arora ,  Wayne P. Burleson ,  Indrani Paul ,  Yasuko Eckert

    IPC: H05K7/20

    CPC classification number: H05K7/20809 ,  H05K5/0213

    Abstract: A cooling system controller for a set of computing resources of a data center includes a first interface to couple to a first flow controller that controls a rate of thermal energy transfer to a PCM store from the set of computing resources, a second interface to couple to a second flow controller that controls a rate of thermal energy transfer from the PCM store to a cooling system, and a controller to determine a current set of operational parameters for the data center and to manipulate the first and second flow controllers and via the first and second interfaces to control a net thermal energy transfer to and from the PCM store based on the current set of parameters.

    Abstract translation: 用于数据中心的一组计算资源的冷却系统控制器包括耦合到第一流控制器的第一接口，该第一接口控制从该组计算资源到PCM存储器的热能传输速率，第二接口耦合到 第二流量控制器，其控制从PCM存储器到冷却系统的热能传递速率;以及控制器，用于确定数据中心的当前操作参数集合，并且操纵第一和第二流量控制器，并经由第一和第二流控制器 第二接口，用于基于当前的参数集来控制到/或从PCM存储器的净热能传递。

    Ring networks for intra- and inter-memory I/O including 3D-stacked memories
    28.
    发明授权
    Ring networks for intra- and inter-memory I/O including 3D-stacked memories 有权
    用于内部和内部存储器I / O的环形网络，包括3D堆叠存储器

    公开(公告)号：US09443561B1

    公开(公告)日：2016-09-13

    申请号：US14719200

    申请日：2015-05-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David Roberts ,  Yasuko Eckert ,  Mitesh Meswani ,  Indrani Paul

    IPC: G11C5/02 ,  H04L12/933 ,  G06F13/42 ,  G11C5/06 ,  G06F13/40

    CPC classification number: G11C5/02 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/42 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments are described for a communications interconnect scheme for 3D stacked memory devices. A ring network design is used for networks of memory chips organized as individual devices with multiple dies or wafers. The design comprises a three-tier ring network where each ring serves a different set of memory blocks. One ring or set of rings interconnects memory within a die (inter-bank), a second ring or set of rings interconnects memory across die in a stack (inter-die), and the third ring or set of rings interconnects memory across stacks or chip packages (inter-stack).

    Abstract translation: 针对3D堆叠存储器件的通信互连方案描述了实施例。 环形网络设计用于组织为具有多个管芯或晶片的单独器件的存储器芯片的网络。 该设计包括三层环网，其中每个环服务不同的存储块集合。 一个环或一组环将管芯内的存储器互相互连（第二环或一组环）在堆叠（管芯间）中跨芯片互连存储器，并且第三环或一组环将堆叠互连存储器 芯片封装（堆叠）。

    SCHEDULING APPLICATIONS IN PROCESSING DEVICES BASED ON PREDICTED THERMAL IMPACT
    29.
    发明申请
    SCHEDULING APPLICATIONS IN PROCESSING DEVICES BASED ON PREDICTED THERMAL IMPACT 审中-公开
    基于预测热影响的处理设备中的调度应用

    公开(公告)号：US20160085219A1

    公开(公告)日：2016-03-24

    申请号：US14493189

    申请日：2014-09-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Manish Arora ,  Yasuko Eckert ,  Srilatha Manne

    IPC: G05B15/02 ,  G06N5/04

    CPC classification number: G06N5/04 ,  G06F1/206 ,  G06F1/329 ,  G06F9/4893 ,  Y02D10/24

    Abstract: A processing device includes a plurality of components and a system management unit to selectively schedule an application phase to one of the plurality of components based on one or more comparisons of predictions of a plurality of thermal impacts of executing the application phase on each of the plurality of components. The predictions may be generated based on a thermal history associated with the application phase, thermal sensitivities of the plurality of components, or a layout of the plurality of components in the processing device.

    Abstract translation: 一种处理设备包括多个组件和系统管理单元，用于基于对多个组件中的每一个上执行应用阶段的多个热冲击的预测的一个或多个比较来选择性地将应用阶段调度到多个组件之一 的组件。 可以基于与应用阶段相关联的热历史，多个组件的热敏感性或处理设备中的多个组件的布局来生成预测。

    INTERFACE TO EXPOSE INTERRUPT TIMES TO HARDWARE
    30.
    发明申请
    INTERFACE TO EXPOSE INTERRUPT TIMES TO HARDWARE 审中-公开
    接口展示中断时间到硬件

    公开(公告)号：US20160077575A1

    公开(公告)日：2016-03-17

    申请号：US14488864

    申请日：2014-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Indrani Paul ,  Manish Arora

    IPC: G06F1/32

    CPC classification number: G06F1/3237 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3265 ,  G06F1/3287 ,  G06F9/4825 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A power management controller is used to control power management states of a processing device. A register stores a timer tick value accessible to the power management controller. The timer tick value indicates when an interrupt is to occur in the processing device. The power management controller may use the exposed timer tick value to decide whether to transition between power management states such as an active state, an idle state, and a power-gated state. The timer tick value stored in the register may be modified by an operating system, an application, or software implemented on the processing device.

    Abstract translation: 电源管理控制器用于控制处理设备的电源管理状态。 寄存器存储电源管理控制器可访问的定时器计时值。 定时器计时值表示在处理设备中发生中断的时间。 功率管理控制器可以使用暴露的定时器计时值来决定是否在诸如活动状态，空闲状态和功率门控状态的功率管理状态之间转换。 存储在寄存器中的定时器计时值可以由操作系统，应用或在处理设备上实现的软件来修改。

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