公开(公告)号：US10203604B2

公开(公告)日：2019-02-12

申请号：US14989488

申请日：2016-01-06

Applicant: Applied Materials, Inc.

Inventor： Viachslav Babayan ,  Douglas A. Buchberger, Jr. ,  Qiwei Liang ,  Ludovic Godet ,  Srinivas D. Nemani ,  Daniel J. Woodruff ,  Randy Harris ,  Robert B. Moore

IPC: G03F7/20 ,  H01L21/687

Abstract: Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus described herein include a chamber body defining a processing volume. A pedestal may be disposed within the processing volume and a first electrode may be coupled to the pedestal. A moveable stem may extend through the chamber body opposite the pedestal and a second electrode may be coupled to the moveable stem. In certain embodiments, a fluid containment ring may be coupled to the pedestal and a dielectric containment ring may be coupled to the second electrode.

公开(公告)号：US10095114B2

公开(公告)日：2018-10-09

申请号：US14589987

申请日：2015-01-05

Applicant: Applied Materials, Inc.

Inventor： Kartik Ramaswamy ,  Srinivas D. Nemani

IPC: G03F1/80 ,  G03F7/20 ,  H01J11/22 ,  H01J11/32 ,  H01J37/32 ,  G03F7/26 ,  H05H1/48 ,  H05H1/24

Abstract: A method and apparatus disclosed herein apply to processing a substrate, and more specifically to a method and apparatus for improving photolithography processes. The apparatus includes a chamber body, a substrate support disposed within the chamber body, and an electrode assembly. The substrate support has a top plate disposed above the substrate support, a bottom plate disposed below the substrate support, and a plurality of electrodes connecting the top plate to the bottom plate. A voltage is applied to the plurality of electrodes to generate an electric field. Methods for exposing a photoresist layer on a substrate to an electric field are also disclosed herein.

公开(公告)号：US20180144959A1

公开(公告)日：2018-05-24

申请号：US15360412

申请日：2016-11-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Srinivas D. Nemani ,  Gautam Pisharody ,  Seshadri Ramaswami ,  Shambhu N. Roy ,  Niranjan Kumar

IPC: H01L21/67 ,  H01L21/683 ,  G01R29/12

CPC classification number: H01L21/67288 ,  G01R29/12 ,  H01L21/67253 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/6838

Abstract: An electrostatic chucking force tool is described that may be used on workpiece carriers for micromechanical and semiconductor processing. One example includes a workpiece fitting to hold a workpiece when gripped by an electrostatic chucking force by an electrostatic chuck, an arm coupled to the workpiece fitting to pull the workpiece through the workpiece fitting laterally across the chuck, and a force gauge coupled to the arm to measure an amount of force with which the workpiece fitting is pulled by the arm in order to move the workpiece.

公开(公告)号：US09978596B2

公开(公告)日：2018-05-22

申请号：US15377629

申请日：2016-12-13

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Uday Mitra ,  Praburam Gopalraja ,  Srinivas D. Nemani ,  Hua Chung

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

公开(公告)号：US20180051368A1

公开(公告)日：2018-02-22

申请号：US15600247

申请日：2017-05-19

Applicant: Applied Materials, Inc.

Inventor： Jingjing Liu ,  Zhong Qiang Hua ,  Adolph Miller Allen ,  Michael W. Stowell ,  Srinivas D. Nemani ,  Chentsau Ying ,  Bhargav Citla ,  Viachslav Babayan ,  Andrej Halabica

IPC: C23C14/06 ,  C23C14/35 ,  C23C14/34 ,  C23C14/54 ,  H01J37/34 ,  H01L21/02

CPC classification number: C23C14/0605 ,  C23C14/3485 ,  C23C14/35 ,  C23C14/354 ,  C23C14/541 ,  C23C14/542 ,  H01J37/32724 ,  H01J37/3426 ,  H01J37/3435 ,  H01J37/3452 ,  H01J37/3467 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/0332 ,  H01L21/31144

Abstract: A deposited amorphous carbon film includes at least 95% carbon. A percentage of sp3 carbon-carbon bonds present in the amorphous carbon film exceeds 30%, and a hydrogen content of the amorphous carbon film is less than 5%. A process of depositing amorphous carbon on a workpiece includes positioning the workpiece within a process chamber and positioning a magnetron assembly adjacent to the process chamber. The magnetron assembly projects a magnetic field into the process chamber. The method further includes providing a carbon target such that the magnetic field extends through the carbon target toward the workpiece. The method further includes providing a source gas to the process chamber, and providing pulses of DC power to a plasma formed from the source gas within the process chamber. The pulses of DC power are supplied in pulses of 40 microseconds or less, that repeat at a frequency of at least 4 kHz.

公开(公告)号：US09896770B2

公开(公告)日：2018-02-20

申请号：US15383556

申请日：2016-12-19

Applicant: Applied Materials, Inc.

Inventor： Benjamin Schmiege ,  Nitin K. Ingle ,  Srinivas D. Nemani ,  Jeffrey W. Anthis ,  Xikun Wang ,  Jie Liu ,  David Benjaminson

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C25F3/00 ,  C23F1/12 ,  H01J37/32

CPC classification number: C23F1/12 ,  C23F4/00 ,  C30B33/12 ,  H01J37/32009 ,  H01J2237/334

Abstract: Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.

公开(公告)号：US20170309515A1

公开(公告)日：2017-10-26

申请号：US15137245

申请日：2016-04-25

Applicant: APPLIED MATERIALS, INC.

Inventor： He Ren ,  Jie Zhou ,  Guannan Chen ,  Michael W. Stowell ,  Bencherki Mebarki ,  Mehul Naik ,  Srinivas D. Nemani ,  Nikolaos Bekiaris ,  Zhiyuan Wu

IPC: H01L21/768

CPC classification number: H01L21/76883 ,  H01L21/28556 ,  H01L21/76877 ,  H01L23/53209

Abstract: An integrated circuit is fabricated by chemical vapor deposition or atomic layer deposition of a metal film to metal film.

公开(公告)号：US09721807B2

公开(公告)日：2017-08-01

申请号：US15080117

申请日：2016-03-24

Applicant: Applied Materials, Inc.

Inventor： Qingjun Zhou ,  Jungmin Ko ,  Tom Choi ,  Sean Kang ,  Jeremiah Pender ,  Srinivas D. Nemani ,  Ying Zhang

IPC: H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

公开(公告)号：US20170203364A1

公开(公告)日：2017-07-20

申请号：US15326910

申请日：2015-07-16

Applicant: Applied Materials, Inc.

Inventor： Kartik Ramaswamy ,  Anantha K. Subramani ,  Kasiraman Krishnan ,  Jennifer Y. Sun ,  Srinivas D. Nemani ,  Thomas B. Brezoczky ,  Christopher A. Rowland ,  Simon Yavelberg ,  Swaminathan Srinivasan ,  Nag B. Patibandla ,  Ellie Y. Yieh ,  Hou T. Ng

IPC: B22F3/105 ,  B33Y30/00 ,  B33Y50/02 ,  B28B1/00 ,  B23K26/70 ,  B23K10/02 ,  B23K10/00 ,  B23K26/342 ,  B23K26/00 ,  B33Y10/00 ,  B22F1/00

CPC classification number: B22F3/1055 ,  B22F1/0003 ,  B22F2003/1051 ,  B22F2003/1057 ,  B22F2202/13 ,  B22F2301/205 ,  B22F2998/10 ,  B23K10/006 ,  B23K10/027 ,  B23K26/0006 ,  B23K26/342 ,  B23K26/702 ,  B23K2103/14 ,  B28B1/001 ,  B29C64/153 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y50/02 ,  G05B2219/49007

Abstract: An additive manufacturing system includes a platen, a feed material dispenser apparatus configured to deliver a feed material over the platen, a laser configured to produce a laser beam, a controller configured to direct the laser beam to locations specified by data stored in a computer-readable medium to cause the feed material to fuse, and a plasma source configured to produce ions that are directed to substantially the same location on the platen as the laser beam.

公开(公告)号：US09514953B2

公开(公告)日：2016-12-06

申请号：US14541978

申请日：2014-11-14

Applicant: Applied Materials, Inc.

Inventor： Chia-Ling Kao ,  Sean Kang ,  Jeremiah T. Pender ,  Srinivas D. Nemani ,  He Ren ,  Mehul Naik

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/32834 ,  H01J37/32871 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中，提供了用于蚀刻阻挡层低k层的方法。 该方法包括（a）将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分，和（b）化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物，其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体，或至少包含氢气和三氟化氮气体。