公开(公告)号：US08778736B2

公开(公告)日：2014-07-15

申请号：US12192367

申请日：2008-08-15

申请人： Sampath Purushothaman ,  Anna W. Topol

发明人： Sampath Purushothaman ,  Anna W. Topol

IPC分类号： H01L21/00

CPC分类号： H01L21/0217 ,  H01L21/02126 ,  H01L21/02266 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3164 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/45147 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/48

摘要： A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US20130307139A1

公开(公告)日：2013-11-21

申请号：US13443418

申请日：2012-04-10

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/08 ,  H01L24/12 ,  H01L24/80 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24545 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2924/00012 ,  H01L2924/0001 ,  H01L2924/00

摘要： Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric, as well as related structures, are disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

摘要翻译： 公开了包括金属电介质图案在表面上与在电介质上方凸起的金属以及相关结构的接合。 一种方法包括在其表面上提供具有金属 - 电介质图案的第一基板; 提供在其表面上具有金属 - 电介质图案的第二基板; 执行导致金属在电介质上方升高的过程; 清洗金属; 以及将所述第一基板接合到所述第二基板。 还公开了相关的结构。 凸起金属的结合提供了强大的粘合介质，以及良好的电气和热连接，能够创建具有增强功能的三维集成结构。

公开(公告)号：US08492869B2

公开(公告)日：2013-07-23

申请号：US13571920

申请日：2012-08-10

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/50

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.

摘要翻译： 提供了3D集成电路结构。 3D集成电路结构包括接口晶片，其包括第一布线层，包括有源电路的第一有源电路层和包括有源电路的晶片。 第一有源电路层面向下接合到接口晶片，并且晶片正面朝下地接合到第一有源电路层。 第一有源电路层比晶片成本低。

公开(公告)号：US08415248B2

公开(公告)日：2013-04-09

申请号：US13474349

申请日：2012-05-17

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US08399336B2

公开(公告)日：2013-03-19

申请号：US12194211

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L25/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/80001 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。 提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。 第一有源电路层晶片比另一个晶片低成本。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US20120309127A1

公开(公告)日：2012-12-06

申请号：US13572037

申请日：2012-08-10

申请人： Mukta G. FAROOQ ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. FAROOQ ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/60

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

摘要翻译： 提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

公开(公告)号：US08314005B2

公开(公告)日：2012-11-20

申请号：US13010004

申请日：2011-01-20

申请人： Sampath Purushothaman ,  Geraud Jean-Michel Dubois ,  Teddie P. Magbitang ,  Willi Volksen ,  Theo J. Frot

发明人： Sampath Purushothaman ,  Geraud Jean-Michel Dubois ,  Teddie P. Magbitang ,  Willi Volksen ,  Theo J. Frot

IPC分类号： H01L21/76

CPC分类号： H01L21/3105 ,  H01L21/02203 ,  H01L21/7682 ,  H01L2221/1047

摘要： In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.

摘要翻译： 在一个示例性实施例中，一种方法包括：提供具有覆盖衬底的第一层的结构，其中第一层包括具有多个孔的电介质材料; 将填充材料施加到第一层的暴露表面; 将结构加热到第一温度以使填充材料均匀地填充多个孔; 在填充所述多个孔之后，在所述结构上执行至少一个处理; 并且在执行所述至少一个处理之后，通过将所述结构加热至第二温度以分解所述填充材料，从所述多个孔中除去所述填充材料。

公开(公告)号：US20120193752A1

公开(公告)日：2012-08-02

申请号：US13016994

申请日：2011-01-29

申请人： Sampath Purushothaman ,  Roy Rongqing Yu

发明人： Sampath Purushothaman ,  Roy Rongqing Yu

IPC分类号： H01L27/12 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11002 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/8013 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81209 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

摘要翻译： 通过这种方法制造的工艺和最终的制品包括将包含硅绝缘体（SOI）的顶部硅晶片中的将底部硅晶片中的底部器件层连接到顶部器件层中的底部器件层所需的通孔形成， 晶圆。 通孔以这样的方式设置，使得它们从顶部晶片的线（MOL）互连的中间延伸到SOI晶片的掩埋氧化物（BOX）层，其中提供了适当的绝缘以将它们与SOI器件层隔离开。

公开(公告)号：US20120149173A1

公开(公告)日：2012-06-14

申请号：US13398481

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。