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    Low cost integrated circuit bonding process
    21.
    发明授权
    Low cost integrated circuit bonding process 失效
    低成本集成电路焊接工艺

    公开(公告)号：US4661192A

    公开(公告)日：1987-04-28

    申请号：US768262

    申请日：1985-08-22

    申请人： Michael B. McShane

    发明人： Michael B. McShane

    IPC分类号： H01L21/60 ,  H05K3/32 ,  H01L23/10 ,  H01R43/02

    CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/321 ,  Y10T29/49121

    摘要： A low cost process for bonding a plurality of integrated circuit die to a variety of die support frames using existing, readily available equipment. Tape automatic bonding (TAB) processes offer a number of new possibilities in the assembly and packaging of integrated circuits. However, the investigation of TAB techniques or the use of TAB techniques on low volume parts is prohibited by the high cost of "bumping" or putting interconnection balls on the chip or the tape leads. The process permits placing balls on the bonding pads of a plurality of die by a wire bonder, cutting off the wire, planarizing the balls, coating the planarized region with a conductive epoxy and then registering and bonding the die to corresponding conductive patterns on die support frames.

    摘要翻译： 使用现有的容易获得的设备将多个集成电路管芯连接到各种管芯支撑框架的低成本工艺。 磁带自动键合（TAB）工艺为集成电路的组装和封装提供了许多新的可能性。 然而，TAB技术的研究或TAB技术在低体积零件上的使用被“撞击”或将互连球放在芯片或磁带引线上的高成本被禁止。 该过程允许通过引线接合机将球放置在多个管芯的接合焊盘上，切断电线，平坦化球，用导电环氧树脂涂覆平坦化区域，然后将管芯配准并结合到管芯支撑件上的对应导电图案 框架。

    STACKED SEMICONDUCTOR DEVICES
    23.
    发明申请
    STACKED SEMICONDUCTOR DEVICES 有权
    堆叠半导体器件

    公开(公告)号：US20130087926A1

    公开(公告)日：2013-04-11

    申请号：US13268580

    申请日：2011-10-07

    申请人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

    发明人： Perry H. Pelley ,  Kevin J. Hess ,  Michael B. McShane

    IPC分类号： H01L23/48 ,  H01L21/78

    CPC分类号： H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06589

    摘要： A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

    摘要翻译： 叠层半导体器件包括第一，第二，第三和第四半导体器件。 每个第一和第二半导体器件的第一主表面包括有源电路直接面对彼此，第三和第四半导体器件的第一主表面包括有源电路直接面对彼此。 第二半导体器件的第二主表面直接面向第三半导体器件的第二主表面。 堆叠的半导体器件包括多个连续的导电通孔，其中每个连续导电通孔从第一器件的第二主表面延伸穿过第一器件，第二器件，第三器件和第四器件到第四器件的第二主表面 设备。 每个半导体器件可以包括在器件的至少一个边缘上的第一主表面处的倾斜边缘。

    Thermally enhanced semiconductor device having exposed backside and method for making the same
    25.
    发明授权
    Thermally enhanced semiconductor device having exposed backside and method for making the same 失效
    具有暴露背面的热增强型半导体器件及其制造方法

    公开(公告)号：US5450283A

    公开(公告)日：1995-09-12

    申请号：US179892

    申请日：1994-01-10

    申请人： Paul T. Lin ,  Michael B. McShane

    发明人： Paul T. Lin ,  Michael B. McShane

    IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H05K7/20

    CPC分类号： H01L21/568 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/18161

    摘要： A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.

    摘要翻译： 描述具有暴露背面（22）的热增强半导体器件（10）。 在一个实施例中，提供在基板的上表面和下表面上具有导电迹线（14）图案的PC板基板（12）。 在具有导电通孔（16）的两个表面之间保持电连续性。 半导体管芯（18）被翻转安装到衬底的上表面。 焊接凸块（26）将管芯电连接到导电迹线，底部填充物（28）将管芯的有效侧（20）连接到衬底的上表面。 围绕模具的周边（24）形成包装体（40），留下非活性背面，以增强散热。 不活动的背面还可以耦合到散热器以增加散热。 电连接到导电迹线的多个焊球（42）附接到基板的下表面。