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    Semiconductor device with a distributed plating pattern
    21.
    发明申请
    Semiconductor device with a distributed plating pattern 审中-公开
    具有分布电镀图案的半导体器件

    公开(公告)号：US20070267759A1

    公开(公告)日：2007-11-22

    申请号：US11435518

    申请日：2006-05-17

    申请人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

    发明人： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Cheemen Yu ,  Hem Takiar

    IPC分类号： H01L23/48

    CPC分类号： H05K3/243 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K3/28 ,  H05K2201/09781 ,  H05K2201/0989 ,  H01L2924/00

    摘要： A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.

    摘要翻译： 公开了一种基板和由其形成的半导体管芯封装，其包括用于减小半导体管芯上的机械应力的分布电镀图案。 根据本发明的实施例的衬底可以包括以双映像电镀工艺电镀的迹线和接触焊盘。 此外，基板可以包括包括电镀材料的虚拟电镀区域。 电镀通孔和/或迹线以及虚拟电镀区域内的电镀材料提供均匀分布在基板表面上的电镀图案。 电镀图案的均匀分布防止成品基板中的峰和谷。

    High density three dimensional semiconductor die package
    27.
    发明授权
    High density three dimensional semiconductor die package 有权
    高密度三维半导体芯片封装

    公开(公告)号：US07663216B2

    公开(公告)日：2010-02-16

    申请号：US11264889

    申请日：2005-11-02

    申请人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    发明人： Cheemen Yu ,  Chih-Chin Liao ,  Hem Takiar

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

    摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个基板上的一组迹线用作地址引脚，并相对于其它基板的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。