公开(公告)号：US5847448A

公开(公告)日：1998-12-08

申请号：US749660

申请日：1996-11-15

Applicant: Christian Val ,  Michel Leroy

Inventor： Christian Val ,  Michel Leroy

IPC: H01L21/98 ,  H01L25/065 ,  H01L23/02 ,  H01L23/34

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/14

Abstract: A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.

Abstract translation: 一种用于互连堆叠半导体板的方法和装置，其中每个板具有集成电路。 半导体板（P）被堆叠并彼此固定。 在一个实施例中，它们的连接触点通过导线（F）连接到除了与印刷电路接触的一个（B）之外的叠层的任何一个面中。 在堆叠的面（FV，FS，FL）上形成板与印刷电路的连接。

公开(公告)号：US5237204A

公开(公告)日：1993-08-17

申请号：US752902

申请日：1991-08-26

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/057 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/642 ,  H01L23/057 ,  H01L23/49827 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15313 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011

Abstract: The invention provides a device for distributing electric potentials for supplying a component with electric power, capable of being incorporated in the case in which the component is encapsulated.This device is in the form of a plate comprising conducting planes connected to external power supply potentials. This plate either forms the cover of the case or is placed inside the case above said component. Each of the conducting planes of the device is connected, outside the case, to the power supply potential and, inside the case, at multiple points to the component so as to distribute these potentials to the appropriate inputs/outputs thereof, thus reducing the number of inputs/outputs of the case.

Abstract translation: 本发明提供了一种用于分配用于提供具有电力的部件的电位的装置，其能够被结合在该部件被封装的情况下。 该装置是包括连接到外部电源电位的导电平面的板的形式。 该板形成壳体的盖或者放置在壳体上方的所述部件上。 设备的每个导电平面在壳体外部连接到电源电位，并且在壳体内部，在多个点处连接到部件，以将这些电位分配到其适当的输入/输出，从而减少数量 的输入/输出。

公开(公告)号：US5002895A

公开(公告)日：1991-03-26

申请号：US431448

申请日：1989-11-03

Applicant: Guy Le Parquier ,  Christian Val

Inventor： Guy Le Parquier ,  Christian Val

IPC: G01R1/04 ,  H01L23/58

CPC classification number: G01R1/04 ,  H01L22/32 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  Y10T29/49004

Abstract: A device and method are disclosed for connecting an electronic component so that it can be tested and mounted. According to the method, pads on the component are first connected to pads on a surrounding frame, by means of conducting wires. The component is tested by probes of the testing instruments to the pads of the surrounding frame. When the tests are done, the component and its frame is placed on the substrate on which it has to be mounted. The pads of the component are connected to pads on the substrate by the wires used for connection to the pads of the surrounding frame. After connection, the wires are cut between the substrate pads and the frame pads, and then the frame is removed.

Abstract translation: 公开了一种用于连接电子部件以使其能够被测试和安装的装置和方法。 根据该方法，元件上的焊盘首先通过导线连接到周围框架上的焊盘。 该组件通过测试仪器的探头测试到周围框架的焊盘。 当测试完成时，组件及其框架放置在必须安装在其上的基板上。 组件的焊盘通过用于连接到周围框架的焊盘的导线连接到衬底上的焊盘。 连接后，在基板焊盘和框架焊盘之间切割电线，然后移除框架。

公开(公告)号：US4559579A

公开(公告)日：1985-12-17

申请号：US571554

申请日：1984-01-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/00 ,  H01L23/64 ,  H02H9/04 ,  H05K1/16 ,  H05K3/34 ,  H05K9/00 ,  H02H3/20

CPC classification number: H05K9/0039 ,  H01L23/647 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/162 ,  H05K1/167 ,  H05K3/3447

Abstract: A device for the protection of an electronic component and/or of a circuit, integrated in the carrier of the latter, against the disturbances (voltages) generated by an external electromagnetic field. It principally comprises an electrical connection (frame) whose conductivity increases considerably under the action of the external field, between each of the outlet connections of the component which is to be protected. This electrical connection is formed by a varistance and an electrode connected to the earth of the device.

Abstract translation: PCT No.PCP / FR83 / 00091 Sec。 371日期1984年1月3日 102（e）日期1984年1月3日PCT提交1983年5月10日PCT公布。 公开号WO83 / 04157 日期：1983年11月24日。一种用于保护集成在后者的载体中的电子部件和/或电路的装置，用于抵抗由外部电磁场产生的干扰（电压）。 它主要包括电连接（框架），其电导率在外部场的作用下显着增加，在被保护部件的每个出口连接之间。 该电连接由连接到设备的地球的无阻力和电极形成。

公开(公告)号：US08735220B2

公开(公告)日：2014-05-27

申请号：US13377109

申请日：2010-06-14

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00

Abstract: A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.

Abstract translation: 一种用于制造重构晶片的方法，其包括具有连接焊盘的芯片，包括：制造芯片的第一晶片，在所述晶片上制造堆叠的至少一层芯片焊盘重新分布的导电轨道 芯片的互连，该堆叠被指定为主RDL层，切割该晶片以获得各自配备有RDL层的各个芯片，将具有RDL层的各个芯片传递到足够刚性的支撑件，以在下列过程中保持平坦 步骤，该支撑件配备有粘合剂层，RDL层在粘合剂层上，沉积树脂以封装芯片，聚合树脂，去除刚性载体，按顺序沉积单个再分布层，称为小型RDL 将主RDL层的导电轨道连接到互连触点，通过在粘合剂层中制成的孔，晶片包括 聚合树脂，具有RDL层的芯片和小型RDL是重新构建的晶片。

公开(公告)号：US08546190B2

公开(公告)日：2013-10-01

申请号：US13255874

申请日：2010-03-09

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

Abstract translation: 一种用于制造重构晶片的方法，其包括具有在芯片前侧上的连接焊盘的芯片，该过程包括将芯片定位在粘合剂支撑件上，正面朝下放置在支撑体上; 将树脂沉积在载体上以封装芯片; 并固化树脂。 在沉积树脂之前，该工艺包括将用于定位芯片的支撑晶片连接到芯片上，该支撑晶片具有放置在芯片一侧的部件。

公开(公告)号：US08359740B2

公开(公告)日：2013-01-29

申请号：US13140637

申请日：2009-12-18

Applicant: Christian Val ,  Pascal Couderc ,  Alexandre Val

Inventor： Christian Val ,  Pascal Couderc ,  Alexandre Val

IPC: H05K3/30

CPC classification number: H01L21/6835 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/141 ,  H05K1/185 ,  H05K3/321 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/0401

Abstract: A process for the wafer-scale fabrication of CMS electronic modules starts from a wafer with metallized outputs, comprising electronic components molded in resin and, on one side, the external outputs of the electronic components on which a nonoxidizable metal or alloy is deposited, and of a printed circuit provided with oxidizable metal or alloy contact pads. In the process, the wafer is cut in predetermined patterns for obtaining reconfigured molded components that include at least one electronic component; the reconfigured components are assembled on the printed circuit, the metallized external outputs of the reconfigured components being placed opposite the metallized contact pads of the printed circuit; and these external outputs are connected solderlessly to the metallized contact pads of the printed circuit by means of a material based on an electrically conductive adhesive or ink.

Abstract translation: 用于晶片尺寸制造CMS电子模块的工艺从具有金属化输出的晶片开始，包括以树脂模制的电子部件，以及在一侧上沉积有不可氧化的金属或合金的电子部件的外部输出，以及 设置有可氧化金属或合金接触垫的印刷电路。 在该过程中，以预定图案切割晶片以获得包括至少一个电子部件的重新配置的模制部件; 重新配置的组件被组装在印刷电路上，重新配置的组件的金属化的外部输出与印刷电路的金属化接触焊盘相对放置; 并且这些外部输出通过基于导电粘合剂或墨水的材料无焊地连接到印刷电路的金属化接触焊盘。

公开(公告)号：US08264853B2

公开(公告)日：2012-09-11

申请号：US12095157

申请日：2006-11-30

Applicant: Christian Val ,  Olivier Lignier

Inventor： Christian Val ,  Olivier Lignier

IPC: H01R12/16

CPC classification number: H05K1/144 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/19041 ,  H01L2924/3512 ,  H05K1/185

Abstract: The invention relates to a 3D electronic module comprising a stack (100) of at least a first slice (10) and a second slice (30), the first slice (10) having on a face (101) at least one set (4) of electrically conductive protrusions (41), and the second slice (30) comprising at least one zone (61) of electrically insulating material, traversing the thickness of the slice. The second slice (30) comprises at least one electrically conductive element (3) traversing said slice in a zone (61) of electrically insulating material, able to receive a set (4) of protrusions (41) of the first slice (10).

Abstract translation: 本发明涉及一种3D电子模块，其包括至少第一切片（10）和第二切片（30）的堆叠（100），所述第一切片（10）在面部（101）上具有至少一组 ），并且所述第二切片（30）包括穿过所述切片的厚度的至少一个电绝缘材料区（61）。 第二切片（30）包括穿过电绝缘材料区域（61）中的所述切片的至少一个导电元件（3），能够接收第一切片（10）的一组（4）突起（41） 。

公开(公告)号：US08136237B2

公开(公告)日：2012-03-20

申请号：US12522426

申请日：2008-01-28

Applicant: Christian Val

Inventor： Christian Val

IPC: H05K3/36

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract translation: 本发明涉及一种将第一晶片（T1）的电子部件与第二晶片（T2）的电子部件互连的方法，每个晶片具有在厚度方向上穿过晶片的金属化通孔（1）。 该方法包括在第一晶片（T1）的每个通孔（1）上沉积含有溶剂的导电油墨滴（3）; 在第一晶片（T1）的通孔（1）上基本上重叠第二晶片（T2）的第一晶片（T2）的堆叠，使得第二晶片（T2）的通孔（1） 通过加热或施加真空去除包含在液滴（3）中的50至90％的溶剂，以获得糊状油墨; 和糊状墨滴（3）的激光烧结，以在叠置的金属化通孔（1）之间产生电连接（31）。

公开(公告)号：US20110312132A1

公开(公告)日：2011-12-22

申请号：US13255874

申请日：2010-09-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/4334 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/24137 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

Abstract translation: 一种用于制造重构晶片的方法，该晶片包括在芯片的前侧上具有连接焊盘的芯片，该过程包括将芯片定位在粘合剂支撑件上，正面朝下放置在支撑体上; 将树脂沉积在载体上以封装芯片; 并固化树脂。 在沉积树脂之前，该工艺包括将用于定位芯片的支撑晶片连接到芯片上，该支撑晶片具有放置在芯片一侧的部件。