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237 条记录 (耗时 0.025 秒)

    Redundant input/output driver circuit
    21.
    发明授权
    Redundant input/output driver circuit 失效
    冗余输入/输出驱动电路

    公开(公告)号：US06177809B1

    公开(公告)日：2001-01-23

    申请号：US09322470

    申请日：1999-05-28

    申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

    IPC分类号： H03K19094

    CPC分类号： H03K19/00384 ,  H03K19/0005

    摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

    摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。

    Structures for wafer level test and burn-in
    23.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06426904B2

    公开(公告)日：2002-07-30

    申请号：US09803500

    申请日：2001-03-09

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Complementary depletion switch body stack off-chip driver
    25.
    发明授权
    Complementary depletion switch body stack off-chip driver 失效
    互补耗尽开关体堆栈片外驱动

    公开(公告)号：US06177818B1

    公开(公告)日：2001-01-23

    申请号：US09303508

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Claude L. Bertin ,  Anthony R. Bonaccio ,  Howard L. Kalter ,  Thomas M. Maffitt ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H03B2100

    CPC分类号： H03K19/09482 ,  H03K19/00361 ,  H03K19/018521

    摘要： An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.

    摘要翻译： 包括增强型PFET，耗尽型PFET，耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极，并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极，并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中，添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动，则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS，但使设备处于线性模式。

    Integrated circuit capacitor
    26.
    发明授权
    Integrated circuit capacitor 失效
    集成电路电容

    公开(公告)号：US06437385B1

    公开(公告)日：2002-08-20

    申请号：US09607094

    申请日：2000-06-29

    申请人： Claude L. Bertin ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

    发明人： Claude L. Bertin ,  Thomas M. Maffitt ,  Wilbur D. Pricer ,  William R. Tonti

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L27/10832 ,  H01L28/55 ,  H01L28/87 ,  H01L29/66181 ,  H01L29/945

    摘要： Use of different materials for different conductive films forming plates or electrodes of one or more capacitors formed in a trench in a body of semiconductor materials allow connections to be made selectively to the plates. The films may be undercut by different etchants at respective connection apertures to avoid formation of connections or connections made by doped polysilicon of different conductivities forming connections to some plates of similarly doped polysilicon and blocking diode junctions with oppositely doped polysilicon. The blocking diodes may include a compensation implant to adjust reverse breakdown characteristics and provide transient and electrostatic discharge protection.

    摘要翻译： 对于形成在半导体材料体中的沟槽中的一个或多个电容器形成板或不同导电膜的不同材料的使用允许选择性地连接板。 这些膜可能在相应的连接孔处被不同的蚀刻剂削弱，以避免由不同导电性的掺杂多晶硅形成的连接或连接形成连接到具有相反掺杂多晶硅的类似掺杂多晶硅和阻塞二极管结的某些平板。 阻塞二极管可以包括补偿注入以调整反向击穿特性并提供瞬态和静电放电保护。

    Carrier for test, burn-in, and first level packaging
    28.
    发明授权
    Carrier for test, burn-in, and first level packaging 失效
    用于测试，老化和一级包装的载体

    公开(公告)号：US07394268B2

    公开(公告)日：2008-07-01

    申请号：US11531140

    申请日：2006-09-12

    申请人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    发明人： Claude L. Bertin ,  Wayne F. Ellis ,  Mark W. Kellogg ,  William R. Tonti ,  Jerzy M. Zalesinski ,  James M. Leas ,  Wayne J. Howell

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

    摘要翻译： 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

    Electronic fuse structure and method of manufacturing
    29.
    发明授权
    Electronic fuse structure and method of manufacturing 有权
    电子熔断器结构及制造方法

    公开(公告)号：US06633055B2

    公开(公告)日：2003-10-14

    申请号：US09303509

    申请日：1999-04-30

    申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Max G. Levy ,  Timothy D. Sullivan ,  William R. Tonti

    发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Max G. Levy ,  Timothy D. Sullivan ,  William R. Tonti

    IPC分类号： H01L2974

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gap conductor structure for an integrated electronic circuit that may function as an electronic fuse device or as a low capacitance inter level signal line is integrated as part of the semi-conductor chip wiring. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to melt a part of the conducting line. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer. Furthermore, conducting structures completely or partially exposed in the air gap may function as low capacitance minimum delay transmission lines.

    摘要翻译： 作为半导体芯片布线的一部分，集成电子电路的可用作电子熔断器件或低电容级间信号线的间隙导体结构被集成。 间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。 或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。 当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导线中产生更高的热流，从而熔化导电线的一部分。 间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。 此外，在气隙中完全或部分暴露的导电结构可用作低电容最小延迟传输线