公开(公告)号：US20140353795A1

公开(公告)日：2014-12-04

申请号：US13904626

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Huang Liu ,  HongLiang Shen ,  Jin Ping Liu ,  Seung Kim

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括蚀刻设置在两个相邻散热片之间的STI沟槽中的增强的高纵横比工艺（eHARP）氧化物填充物，以形成凹陷的eHARP氧化物填充物。 两个相邻的翅片从体半导体衬底延伸。 覆盖凹陷的eHARP氧化物填充物形成硅层。 将硅层转化为热氧化物层，以进一步用氧化物材料填充STI沟槽。

公开(公告)号：US20160190130A1

公开(公告)日：2016-06-30

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹陷之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US09368342B2

公开(公告)日：2016-06-14

申请号：US14252447

申请日：2014-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Huang Liu ,  Jin Ping Liu

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/306

CPC classification number: H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

Abstract translation: 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

公开(公告)号：US20160163830A1

公开(公告)日：2016-06-09

申请号：US14560035

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hong Yu ,  Jin Ping Liu ,  Haigou Huang ,  Huang Liu

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02326 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在翅片上形成占位符门结构。 占位符门结构包括在占位符材料的顶表面上限定的占位符材料和盖结构。 盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。 在第二盖层的至少一部分上进行氧化处理，以在第二盖层的剩余部分上方形成氧化区域。 去除氧化区域的一部分以露出剩余部分。 去除第二盖层的剩余部分。 移除第一盖层以露出占位符材料。 占位符材料被导电材料代替。

公开(公告)号：US09196710B2

公开(公告)日：2015-11-24

申请号：US14177800

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Jin Ping Liu ,  Shao Ming Koh ,  Amaury Gendron

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Abstract translation: 提供了具有松散硅和锗翅片的集成电路以及用于制造这种集成电路的方法。 该方法包括形成覆盖晶体硅衬底的晶体硅和锗复合层，其中复合层晶格被放宽。 在复合层中形成翅片，并且在翅片上形成栅极。 翅片的一部分在栅极的相对侧上被去除以形成漏腔和源腔，并且源极和漏极分别形成在源极腔和漏极腔中。

公开(公告)号：US09129987B2

公开(公告)日：2015-09-08

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Jin Ping Liu ,  Guillaume Bouche ,  Andy Wei ,  Lakshmanan H. Vanamurthy ,  Cuiqin Xu ,  Sridhar Kuchibhatla ,  Rama Kambhampati ,  Xiuyu Cai

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧上沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US09040380B2

公开(公告)日：2015-05-26

申请号：US14023558

申请日：2013-09-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiang Hu ,  Jin Ping Liu ,  Jill Hildreth ,  Taejoon Han

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/845

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括提供覆盖半导体衬底的翅片结构。 翅片结构限定了在垂直于横向方向的纵向方向上延伸的翅片轴线，并且具有平行于翅片轴线的两个翅片侧壁。 该方法包括形成覆盖翅片结构并横向于翅片轴线的栅极结构。 此外，该方法包括在翅片结构上生长外延材料并限制外延材料在横向上的生长。

公开(公告)号：US20140264613A1

公开(公告)日：2014-09-18

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。

公开(公告)号：US09673039B2

公开(公告)日：2017-06-06

申请号：US14666787

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shishir Ray ,  Yiqun Liu ,  Jin Ping Liu ,  Fabio D'Addamio ,  Sandeep Gaan

IPC: H01L21/316 ,  H01L21/02 ,  H01L21/28 ,  C23C16/30 ,  G11C11/22 ,  H01L29/51

CPC classification number: H01L21/02181 ,  C23C16/308 ,  G11C11/22 ,  H01L21/02189 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 Å thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfO2 and/or tetragonal phase ZrO2. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

公开(公告)号：US09595493B2

公开(公告)日：2017-03-14

申请号：US14822597

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Huang Liu ,  Haigou Huang ,  Jiehui Shu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/321

CPC classification number: H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

Abstract: Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

Abstract translation: 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。