公开(公告)号：US20090140409A1

公开(公告)日：2009-06-04

申请号：US12327649

申请日：2008-12-03

申请人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Dai Sasaki

发明人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Dai Sasaki

IPC分类号： H01L23/48

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor device includes a substrate having bumps on the backside thereof, a first semiconductor chip mounted on the surface of the substrate, a second semiconductor chip mounted on the first semiconductor chip above the surface of the substrate, a first bonding wire having a length L1 for connecting the first semiconductor chip to the substrate, a second bonding wire having a length L2 (where L2>L1) for connecting the second semiconductor chip to the substrate, a first resin seal having a dielectric constant ε1 for sealing the first bonding wire, and a second resin seal having a dielectric constant ε2 (where ε2

摘要翻译： 半导体器件包括其背面具有凸块的衬底，安装在衬底表面上的第一半导体芯片，安装在衬底表面上的第一半导体芯片上的第二半导体芯片，具有长度L1 为了将第一半导体芯片连接到基板，具有用于将第二半导体芯片连接到基板的长度L2（其中L2> L1）的第二接合线，具有用于密封第一接合线的介电常数ε1的第一树脂密封件， 以及具有用于密封第二接合线的介电常数ε2（其中ε2 <ε1）的第二树脂密封件。 长度L1和L2之间的关系以及介电常数ε1和ε2由ε1= epsilon2（L2 / L1）2的等式定义。

公开(公告)号：US20070033553A1

公开(公告)日：2007-02-08

申请号：US11495711

申请日：2006-07-31

申请人： Mitsuaki Katagiri ,  Takashi Iida ,  Hiroya Shimizu ,  Satoshi Isa

发明人： Mitsuaki Katagiri ,  Takashi Iida ,  Hiroya Shimizu ,  Satoshi Isa

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  H05K1/115 ,  H05K3/0005

摘要： System, method and program for inductance analysis for reducing time for analysis, to cope with increase in the system size, to achieve high accuracy in the analysis. Information on a power supply plane, in a state in which a beginning point of non-coupled current of return current accompanying a signal current is placed in the vicinity of a signal through-hole on the power supply plane, based on position information of said signal through-hole, is received. Potential distribution in the power supply plane is determined and output. The non-coupled inductance from the signal through-hole to the power supply through-hole in the power supply plane is evaluated. In the potential analysis, non-coupled inductance L from the signal through-hole to the power supply through-hole is represented by resistance R. The relationship that a voltage increment ΔV is represented by the product of the non-coupled inductance L and the rate of time change of the current, ΔV=LΔI/Δt, is replaced by the relationship that the voltage V is represented by the product of resistance R and non-coupled current I, V=R×I. Potential analysis is performed by analyzing two-dimensional heat diffusion in the power supply plane assuming that a heat source is placed at a beginning point of the non-coupled current.

摘要翻译： 用于电感分析的系统，方法和程序，用于减少分析时间，以应对系统尺寸的增加，在分析中达到高精度。 基于所述电源平面的位置信息，在电源平面的信息通过孔附近，在电源平面附近的信号通孔附近设置电源面的信息， 信号通孔，被接收。 确定并输出电源平面中的电位分布。 评估从信号通孔到电源平面中电源通孔的非耦合电感。 在电位分析中，由电阻R表示从信号通孔到电源通孔的非耦合电感L.电压增量DeltaV由非耦合电感L和 电流的时间变化DeltaV = LDeltaI / Deltat由电压R和非耦合电流I，V = RxI的乘积表示的电压代替。 假设热源位于非耦合电流的起始点，通过分析供电平面中的二维热扩散来执行潜在分析。

公开(公告)号：US20060249842A1

公开(公告)日：2006-11-09

申请号：US11391449

申请日：2006-03-29

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

公开(公告)号：US09589921B2

公开(公告)日：2017-03-07

申请号：US14773817

申请日：2014-03-10

申请人： PS4 Luxco S.a.r.l. ,  Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

发明人： Mitsuaki Katagiri ,  Yu Hasegawa ,  Satoshi Isa

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/12 ,  H01L21/56 ,  H01L21/66 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC分类号： H01L24/17 ,  H01L21/561 ,  H01L22/32 ,  H01L23/12 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83862 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/025 ,  H05K1/141 ,  H05K1/185 ,  H05K2201/10734 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.

摘要翻译： 在一个半导体器件中，半导体芯片具有设置在其主表面上的第一和第二焊盘电极，覆盖半导体芯片的主表面的绝缘膜，布置在绝缘膜之间的再布线层和多​​个外部端子 设置在绝缘膜的顶部。 第一焊盘电极和第二焊盘电极的平面尺寸彼此不同，并且第一焊盘电极和第二焊盘电极经由重新布线层连接到多个外部端子中的任何一个。

公开(公告)号：US08243465B2

公开(公告)日：2012-08-14

申请号：US12707996

申请日：2010-02-18

申请人： Satoshi Itaya ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

发明人： Satoshi Itaya ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Dai Sasaki

IPC分类号： H01R9/00 ,  H01L23/02

CPC分类号： H05K1/181 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.

摘要翻译： 在数据输出电路中，半导体器件减少了用于提供具有电源电压或接地电压以及数据信号传输加速的数据输出电路的电路的布线的阻抗。 附加的基板2a，2b位于半导体芯片1的上表面上。形成在各个附加基板2a，2b上的用于电源10d的第一附加布线层和用于接地的第一附加布线层10形成半导体芯片1上规定的导电区域。 源极配线40C1d或第一接地配线40C1通过附加配线层10d和10s相互连接。 与DQ系统信号线40CDQ相同的方向延伸的第二电源配线40C2d和第二接地配线40C2s形成反馈电流路径。 第二电源配线40C2d和第二接地配线40C2s配置在与DQ系统信号配线40CDQ相邻的位置。

公开(公告)号：US07538431B2

公开(公告)日：2009-05-26

申请号：US12126681

申请日：2008-05-23

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Fumiyuki Osanai

IPC分类号： H01L23/48

CPC分类号： H01L23/5286 ,  H01L23/3114 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.

摘要翻译： 公开了一种半导体器件，其包括数据族焊盘布局，其中努力设计电源引线和接地引线的布局，以将焊盘和焊球焊盘之间的引线的长度优先于最小化有效电感 的半导体芯片。 焊盘布局排列成两行，并且焊盘布局的一个单位被配置为使得数据电源和接地彼此相邻或者在数据电源和地之间插入一个数据。 这样的配置减少数据电源之间的互感，并增加数据电源和地之间的互感，从而导致数据电源与地之间的有效电感的降低，从而导致功率和接地噪声的最小化。

公开(公告)号：US20070164435A1

公开(公告)日：2007-07-19

申请号：US11613914

申请日：2006-12-20

申请人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Fumiyuki Osanai

发明人： Kazutaka Koshiishi ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Fumiyuki Osanai

IPC分类号： H01L23/52

CPC分类号： H01L23/66 ,  H01L23/49822 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/024 ,  H05K3/4688 ,  H05K2201/09309 ,  H01L2924/00

摘要： To reduce noise between a power supply wiring and ground wiring especially in a small, high-density semiconductor device for high-speed operation. A semiconductor device having a second dielectric layer 5 made of dielectric material of which the dielectric loss tan 6 is at least 0.2 and interposed between a power supply wiring layer 6 electrically connected to a semiconductor chip and a ground wiring layer 4, so composed that a dielectric loss generated in the second dielectric layer 5 acts as a low pass filter of the power supply wiring layer 6, and having a first dielectric layer 3 made of dielectric material whose dielectric loss is less than the dielectric loss tan 6 of the second dielectric layer 5 and interposed between a signal wiring layer 2 electrically connected to the semiconductor chip and the ground wiring layer 4.

摘要翻译： 为了降低电源布线和接地布线之间的噪音，特别是在高速运行的小型，高密度半导体器件中。 一种半导体器件，具有由绝缘材料制成的介电损耗tanδ为0.2以上且介于与半导体芯片电连接的电源布线层6和接地布线层4之间的第二介质层5， 在第二电介质层5中产生的介电损耗用作电源布线层6的低通滤波器，并且具有由介电损耗小于第二介电层的介电损耗tanδ的电介质材料制成的第一电介质层3 插入在与半导体芯片电连接的信号布线层2和接地布线层4之间。

公开(公告)号：US20070085214A1

公开(公告)日：2007-04-19

申请号：US11535750

申请日：2006-09-27

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Toru Chonan ,  Shigeyuki Nakazawa

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Toru Chonan ,  Shigeyuki Nakazawa

IPC分类号： H01L23/48

CPC分类号： H01L27/10897 ,  H01L23/49838 ,  H01L23/50 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.

摘要翻译： 半导体器件具有可用作4位，8位和16位结构器件中的任何一个的半导体芯片，以及用于封装半导体芯片的封装。 半导体芯片具有用于所述16位结构器件的DQ系统焊盘的第一和第二DQ焊盘组。 第一DQ焊盘组布置在半导体芯片的表面的中间部分附近的第一区域中，而第二DQ焊盘组布置在表面上的第一区域的外侧的第二区域中。 在第二区域中形成除了包括在第二DQ垫组中的焊盘之外的作为用于8位结构器件的DQ系统焊盘之一的附加焊盘。

公开(公告)号：US07956470B2

公开(公告)日：2011-06-07

申请号：US11535750

申请日：2006-09-27

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Toru Chonan ,  Shigeyuki Nakazawa

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Toru Chonan ,  Shigeyuki Nakazawa

IPC分类号： H01L23/48

CPC分类号： H01L27/10897 ,  H01L23/49838 ,  H01L23/50 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.

摘要翻译： 半导体器件具有可用作4位，8位和16位结构器件中的任何一个的半导体芯片，以及用于封装半导体芯片的封装。 半导体芯片具有用于所述16位结构器件的DQ系统焊盘的第一和第二DQ焊盘组。 第一DQ焊盘组布置在半导体芯片的表面的中间部分附近的第一区域中，而第二DQ焊盘组布置在表面上的第一区域的外侧的第二区域中。 在第二区域中形成除了包括在第二DQ垫组中的焊盘之外的作为用于8位结构器件的DQ系统焊盘之一的附加焊盘。

公开(公告)号：US07875986B2

公开(公告)日：2011-01-25

申请号：US11822265

申请日：2007-07-03

申请人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

发明人： Satoshi Isa ,  Mitsuaki Katagiri ,  Kyoichi Nagata ,  Seiji Narui

IPC分类号： H01L29/40

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Disclosed is a semiconductor memory device in which pads on a chip which are wire-bonded to lands for solder-balls of a package, respectively, are arranged on first and second sides of the chip facing to each other and are disposed on a third side of the chip as well. Four sets of the pads for data signals are respectively disposed on four regions obtained by dividing the first and second sides into the four regions. Pads for command/address signals are arranged on the third side, thereby increasing layout space for bond fingers for the data signals and achieving uniformity in wiring for data signals.

摘要翻译： 公开了一种半导体存储器件，其中芯片上的焊盘分别焊接到封装的焊球的焊盘上，所述焊盘分别布置在芯片的彼此面对的第一和第二侧上，并且设置在第三侧 的芯片以及。 四组用于数据信号的焊盘分别设置在通过将第一和第二侧划分成四个区域而获得的四个区域上。 用于命令/地址信号的板被布置在第三侧上，从而增加了用于数据信号的接合点的布局空间，并实现了数据信号的布线的均匀性。