公开(公告)号：US10978418B2

公开(公告)日：2021-04-13

申请号：US16572626

申请日：2019-09-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/495

Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US10672678B2

公开(公告)日：2020-06-02

申请号：US16431808

申请日：2019-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Heinrich Koerner ,  Michael Bauer ,  Reimund Engl ,  Michael Huettinger ,  Werner Kanert ,  Joachim Mahler ,  Brigitte Ruehle

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/56

Abstract: In various embodiments, methods for forming a chip package are provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.

公开(公告)号：US10600690B2

公开(公告)日：2020-03-24

申请号：US16102174

申请日：2018-08-13

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Claus von Waechter ,  Michael Bauer ,  Holger Doepke ,  Dominic Maier ,  Daniel Porwol ,  Tobias Schmidt

IPC: B32B37/26 ,  B32B38/10 ,  H01L21/78 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  B32B7/027 ,  H05K3/00 ,  B32B7/06

Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.

公开(公告)号：US20180096924A1

公开(公告)日：2018-04-05

申请号：US15821879

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Alfred Haimerl ,  Angela Kessler ,  Wolfgang Schober

IPC: H01L23/498 ,  H01L23/12 ,  H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/492 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/49805 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

公开(公告)号：US20170338169A1

公开(公告)日：2017-11-23

申请号：US15600857

申请日：2017-05-22

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Michael Bauer ,  Jochen Dangelmaier ,  Reimund Engl ,  Johann Gatterbauer ,  Frank Hille ,  Michael Huettinger ,  Werner Kanert ,  Heinrich Koerner ,  Brigitte Ruehle ,  Francisco Javier Santos Rodriguez ,  Antonio Vellei

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02288 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0346 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45611 ,  H01L2224/45618 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45649 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/4567 ,  H01L2224/45671 ,  H01L2224/45672 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/4569 ,  H01L2224/45693 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48507 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2224/85801 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01046 ,  H01L2224/45669 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01056 ,  H01L2924/00 ,  H01L2224/43848

Abstract: In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

公开(公告)号：US20150303135A1

公开(公告)日：2015-10-22

申请号：US14254214

申请日：2014-04-16

Applicant: Infineon Technologies AG

Inventor： Michael Bauer ,  Ludwig Heitzer ,  Christian Stuempfl

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49548 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body.

Abstract translation: 一种制造半导体封装的方法包括提供具有孔径的第一衬底，提供第一半导体芯片，将第一半导体芯片连接到第一衬底，用第一绝缘材料填充孔，并用半导体芯片封装第二绝缘材料 创建第一个封装体。

公开(公告)号：US20130328206A1

公开(公告)日：2013-12-12

申请号：US13966375

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Alfred Haimerl ,  Angela Kessler ,  Michael Bauer

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.