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公开(公告)号:US20210280566A1
公开(公告)日:2021-09-09
申请号:US16809515
申请日:2020-03-04
Applicant: Intel Corporation
Inventor: Suresh V. POTHUKUCHI , Andrew ALDUINO , Ravindranath V. MAHAJAN , Srikant NEKKANTY , Ling LIAO , Harinadh POTLURI , David M. BOND , Sushrutha Reddy GUJJULA , Donald Tiendung TRAN , David HUI , Vladimir TAMARKIN
IPC: H01L25/16 , H01L23/538 , H01L23/367 , H01L23/473 , H01L23/40 , H04Q11/00
Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.
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公开(公告)号:US20210195798A1
公开(公告)日:2021-06-24
申请号:US16723865
申请日:2019-12-20
Applicant: Intel Corporation
Inventor: Nicholas NEAL , Nicholas S. HAEHN , Je-Young CHANG , Kyle ARRINGTON , Aaron MCCANN , Edvin CETEGEN , Ravindranath V. MAHAJAN , Robert L. SANKMAN , Ken P. HACKENBERG , Sergio A. CHAN ARGUEDAS
IPC: H05K7/20 , H01L23/367 , H01L23/00 , H01L23/498
Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.
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公开(公告)号:US20200185289A1
公开(公告)日:2020-06-11
申请号:US16463638
申请日:2016-12-27
Applicant: Intel Corporation
Inventor: Mitul MODI , Robert L. SANKMAN , Debendra MALLIK , Ravindranath V. MAHAJAN , Amruthavalli P. ALUR , Yikang DENG , Eric J. LI
IPC: H01L23/13 , H01L23/498 , H01L23/31 , H01L25/065 , H01L25/18 , H01L25/00 , H01L21/56 , H01L21/48
Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20190267306A1
公开(公告)日:2019-08-29
申请号:US16343703
申请日:2016-12-07
Applicant: Intel Corporation
Inventor: Nachiket R. RARAVIKAR , Ravindranath V. MAHAJAN , Robert L. SANKMAN , James C. MATAYABAS, Jr. , Ken P. HACKENBERG , Nayandeep K. MAHANTA , David D. OLMOZ
IPC: H01L23/373 , H01L23/42 , H01L23/367
Abstract: In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
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公开(公告)号:US20180329240A1
公开(公告)日:2018-11-15
申请号:US15774432
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Vivek RAGHUNATHAN , Mihir K. ROY , Ravindranath V. MAHAJAN
IPC: G02F1/13357 , H05K1/18 , H05K1/02 , H05K3/30 , H01S3/04
CPC classification number: G02F1/1336 , G02F2001/133628 , G06F1/20 , H01S3/0408 , H04B1/38 , H04B1/385 , H05K1/0203 , H05K1/181 , H05K3/303 , H05K2201/10121 , H05K2201/10522
Abstract: Embodiments are generally directed to a self-cooled laser integrated device and substrate architecture. An embodiment of a device includes a substrate or printed circuit board (PCB); a component coupled with the substrate or PCB, the component including an cooling agent on at least one side of the component; one or more laser sources, at least a first laser source of the one or more laser sources being implemented to direct laser light onto the cooling agent; and a controller to drive the laser source, wherein the cooling agent provides cooling for the component when the laser light is directed on the engineered cooling agent.
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公开(公告)号:US20240213156A1
公开(公告)日:2024-06-27
申请号:US18089491
申请日:2022-12-27
Applicant: Intel Corporation
Inventor: Kristof DARMAWIKARTA , Srinivas V. PIETAMBARAM , Gang DUAN , Tarek A. IBRAHIM , Aaron GARELICK , Srikant NEKKANTY , Ravindranath V. MAHAJAN , Rahul N. MANEPALLI
IPC: H01L23/532 , H01L23/00 , H01L23/15 , H01L23/498 , H01L23/522 , H01L23/535 , H01L23/64 , H01L25/065
CPC classification number: H01L23/53209 , H01L23/15 , H01L23/49816 , H01L23/5226 , H01L23/535 , H01L23/642 , H01L24/05 , H01L24/29 , H01L25/0655 , H01L2224/04026 , H01L2224/05567 , H01L2224/29007 , H01L2224/29021 , H01L2224/29101 , H01L2924/1436 , H01L2924/15321
Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.
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公开(公告)号:US20240213132A1
公开(公告)日:2024-06-27
申请号:US18089476
申请日:2022-12-27
Applicant: Intel Corporation
Inventor: Kristof DARMAWIKARTA , Benjamin DUONG , Darko GRUJICIC , Shayan KAVIANI , Mahdi MOHAMMADIGHALENI , Suddhasattwa NAD , Thomas L. SOUNART , Marcel WALL , Ravindranath V. MAHAJAN , Rahul N. MANEPALLI
IPC: H01L23/498 , H01L27/01
CPC classification number: H01L23/49838 , H01L27/016 , H01L28/86 , H01L28/90 , H01L23/49822 , H01L23/49894 , H01L24/16
Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.
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公开(公告)号:US20240145395A1
公开(公告)日:2024-05-02
申请号:US18406018
申请日:2024-01-05
Applicant: Intel Corporation
Inventor: MD Altaf HOSSAIN , Ankireddy NALAMALPU , Dheeraj SUBBAREDDY , Robert SANKMAN , Ravindranath V. MAHAJAN , Debendra MALLIK , Ram S. VISWANATH , Sandeep B. SANE , Sriram SRINIVASAN , Rajat AGARWAL , Aravind DASU , Scott WEBER , Ravi GUTALA
IPC: H01L23/538 , H01L23/00 , H01L25/18
CPC classification number: H01L23/5385 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L25/18 , H01L23/481 , H01L2224/16225
Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
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公开(公告)号:US20240063069A1
公开(公告)日:2024-02-22
申请号:US17892930
申请日:2022-08-22
Applicant: Intel Corporation
Inventor: Brandon C. MARIN , Rahul N. MANEPALLI , Ravindranath V. MAHAJAN , Srinivas V. PIETAMBARAM , Jeremy D. ECTON , Gang DUAN , Suddhasattwa NAD
IPC: H01L23/13 , H01L23/498 , H01L23/15
CPC classification number: H01L23/13 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/15 , H01L24/16
Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.
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公开(公告)号:US20230197574A1
公开(公告)日:2023-06-22
申请号:US18111329
申请日:2023-02-17
Applicant: Intel Corporation
Inventor: Aditya S. VAIDYA , Ravindranath V. MAHAJAN , Digvijay A. RAORANE , Paul R. START
IPC: H01L23/48 , H01L21/768 , H01L23/498 , H01L23/00 , H01L25/16 , H01L23/538 , H01L25/065
CPC classification number: H01L23/481 , H01L21/76898 , H01L23/5385 , H01L23/49827 , H01L24/06 , H01L24/09 , H01L24/83 , H01L25/16 , H01L25/0655 , H01L24/16 , H01L2224/16225 , H01L2224/16237
Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
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